Change in ...coreboot[master]: mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30755

Change subject: mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP
......................................................................

mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP

1) Add a Platform Data Region called SI_PDR which is allocated in the flash
descriptor for this platform
2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile
storage.
3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG
so it is clear they are associated.
4) Move the RW_DIAG region to the start of the RW region so that once we can
re-enable a larger BIOS region this sub-region will be in the uncached area
since it is not accessed on a normal boot.

BUG=b:119435206
TEST=tested on Arcada board to ensure expected regions are present

Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3
Signed-off-by: Duncan Laurie 
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 9 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30755/1

diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 6631769..ba42a6f 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -3,20 +3,25 @@
    	SI_DESC@0x0 0x1000
    	SI_EC@0x1000 0x100000
    	SI_GBE@0x101000 0x2000
-		SI_ME@0x103000 0xefd000
+		SI_ME@0x103000 0xef9000
+		SI_PDR@0xffc000 0x4000
    }
    SI_BIOS@0x1000000 0x1000000 {
-		RW_SECTION_A@0x0 0x280000 {
+		RW_DIAG@0x0 0x6d0000 {
+			DIAG_NVRAM@0x0 0x10000
+			RW_LEGACY(CBFS)@0x10000 0x6c0000
+		}
+		RW_SECTION_A@0x6d0000 0x280000 {
    		VBLOCK_A@0x0 0x10000
    		FW_MAIN_A(CBFS)@0x10000 0x26ffc0
    		RW_FWID_A@0x27ffc0 0x40
    	}
-		RW_SECTION_B@0x280000 0x280000 {
+		RW_SECTION_B@0x950000 0x280000 {
    		VBLOCK_B@0x0 0x10000
    		FW_MAIN_B(CBFS)@0x10000 0x26ffc0
    		RW_FWID_B@0x27ffc0 0x40
    	}
-		RW_MISC@0x500000 0x30000 {
+		RW_MISC@0xbd0000 0x30000 {
    		UNIFIED_MRC_CACHE@0x0 0x20000 {
    			RECOVERY_MRC_CACHE@0x0 0x10000
    			RW_MRC_CACHE@0x10000 0x10000
@@ -29,8 +34,6 @@
    		RW_VPD@0x28000 0x2000
    		RW_NVRAM@0x2a000 0x6000
    	}
-		CONSOLE@0x530000 0x20000
-		RW_LEGACY(CBFS)@0x550000 0x6b0000
    	WP_RO@0xc00000 0x400000 {
    		RO_VPD@0x0 0x4000
    		RO_UNUSED@0x4000 0xc000