Change in coreboot[master]: soc/intel/xeon_sp: Define all SMI_STS bits

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50915 )

Change subject: soc/intel/xeon_sp: Define all SMI_STS bits
......................................................................

soc/intel/xeon_sp: Define all SMI_STS bits

As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.

Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons 
---
M src/soc/intel/xeon_sp/include/soc/pm.h
1 file changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/50915/1

diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h
index 5087e4f..b699e1c 100644
--- a/src/soc/intel/xeon_sp/include/soc/pm.h
+++ b/src/soc/intel/xeon_sp/include/soc/pm.h
@@ -36,12 +36,29 @@
 #define  GBL_SMI_EN		(1 <<  0)
 #define SMI_STS			0x34
 #define  SMI_STS_BITS			32
+#define  XHCI_SMI_STS_BIT		31
+#define  ME_SMI_STS_BIT			30
+#define  SERIAL_IO_SMI_STS_BIT		29
+#define  ESPI_SMI_STS_BIT		28
 #define  GPIO_UNLOCK_SMI_STS_BIT	27
+#define  SPI_SMI_STS_BIT		26
+#define  SCC_SMI_STS_BIT		25
+#define  IE_SMI_STS_BIT			23
+#define  MONITOR_STS_BIT		21
+#define  PCI_EXP_SMI_STS_BIT		20
+#define  SMBUS_SMI_STS_BIT		16
+#define  SERIRQ_SMI_STS_BIT		15
 #define  PERIODIC_STS_BIT		14
 #define  TCO_STS_BIT			13
+#define  DEVMON_STS_BIT			12
+#define  MCSMI_STS_BIT			11
+#define  GPIO_STS_BIT			10
+#define  GPE0_STS_BIT			9
 #define  PM1_STS_BIT			8
+#define  SWSMI_TMR_STS_BIT		6
 #define  APM_STS_BIT			5
 #define  SMI_ON_SLP_EN_STS_BIT		4
+#define  LEGACY_USB_STS_BIT		3
 #define  BIOS_STS_BIT			2
 #define GPE_CNTL		0x42
 #define  SWGPE_CTRL		(1 << 1)