Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62064 )
Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ......................................................................
soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances.
Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register.
SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO.
BUG=b:211954778 TEST=Able to build brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jeff Daly jeffd@silicom-usa.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c 31 files changed, 57 insertions(+), 173 deletions(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Jeff Daly: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 37c0b62..25d11d3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -104,6 +104,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h index b65b24d..98843d1 100644 --- a/src/soc/intel/alderlake/include/soc/pm.h +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -162,9 +162,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index d8308b4..f8b858f 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -133,20 +133,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 91d203e..9e48971 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -107,6 +107,7 @@ select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SOC_INTEL_NO_BOOTGUARD_MSR select SOUTHBRIDGE_INTEL_COMMON_SMBUS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3c0b1e7..1e6a927 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -242,7 +242,4 @@ /* STM Support */ uint16_t get_pmbase(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 79ece4b..fbb2345 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -237,17 +237,3 @@ reg32 |= SLEEP_AFTER_POWER_FAIL; write32p(gen_pmcon1, reg32); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON1); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON1), reg_val); -} diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9517cee..0a61381 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -105,6 +105,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 59b2ba0..d345e07 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void);
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a79d262..38a0ce7 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -127,20 +127,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index bb38204..fc65a08 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -178,6 +178,9 @@ */ void pmc_gpe_init(void);
+/* Clear PMC GEN_PMCON_A register status bits */ +void pmc_clear_pmcon_sts(void); + /* Power Management Utility Functions. */
/* Returns PMC base address */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index fa1a990..effdc12 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -10,6 +10,12 @@
if SOC_INTEL_COMMON_BLOCK_PMC
+config SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION + bool + help + Select this on platforms where the PMC register for PM configuration (i.e., + GEN_PMCON_A/B etc. are memory mapped). + config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index b6a2fc9..51b2aa6 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <intelblocks/acpi.h> #include <intelblocks/pmc.h> +#include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h>
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index da78d5c..a2e3e9e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -5,6 +5,7 @@ #include <assert.h> #include <bootmode.h> #include <device/mmio.h> +#include <device/pci.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <console/console.h> @@ -14,6 +15,7 @@ #include <intelblocks/tco.h> #include <option.h> #include <security/vboot/vboot_common.h> +#include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> #include <string.h> @@ -580,6 +582,44 @@ gpio_route_gpe(dw0, dw1, dw2); }
+#if ENV_RAMSTAGE +static void pmc_clear_pmcon_sts_mmio(void) +{ + uint8_t *addr = pmc_mmio_regs(); + + clrbits32((addr + GEN_PMCON_A), MS4V); +} + +static void pmc_clear_pmcon_sts_pci(void) +{ + struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!dev) + return; + + pci_and_config32(dev, GEN_PMCON_A, ~MS4V); +} + +/* + * Clear PMC GEN_PMCON_A register status bits: + * SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit + */ +void pmc_clear_pmcon_sts(void) +{ + /* + * Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. + * Typically, there are two possible ways to perform GEN_PMCON_A register programming + * (like `pmc_clear_pmcon_sts()`) as: + * 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. + * 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. + */ + if (CONFIG(SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION)) + pmc_clear_pmcon_sts_mmio(); + else + pmc_clear_pmcon_sts_pci(); +} +#endif + void pmc_set_power_failure_state(const bool target_on) { const unsigned int state = get_uint_option("power_on_after_fail", diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index faf7f20..368fac8 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -48,7 +48,4 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index b861513..8d670c6 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -247,18 +247,3 @@ uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
void clear_pmc_status(void) { /* TODO */ } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index a1f7794..b2d322ca 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -58,6 +58,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6ebbbfa..6a86787 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 9bd431d..0109215 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index ae693a4..d884551 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -56,6 +56,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index ad2beff..05db830 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index f552a8c..b7829b2 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 48b735e..e0e0c7b 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index 11d6663..eea875b 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index d9ecb63..fb1aecd 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 51be0eb..f0ce146 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -189,7 +189,4 @@ /* STM Support */ uint16_t get_pmbase(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index ded44dc..fe26ebf 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -265,18 +265,3 @@ reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(dev, GEN_PMCON_B, reg8); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2b673cab..df5c167 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -80,6 +80,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index d62e8ad..cb0781a 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -162,9 +162,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index aee2b3b..e854385 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -132,20 +132,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index 63b15cd..b4d6df9 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -121,7 +121,4 @@
void pmc_lock_smi(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index 14c7da8..c63285c 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -179,18 +179,3 @@ reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -}
-
Felix Held (Code Review)