Change in coreboot[master]: soc/amd/cezanne: Implement PROVIDES_ROM_SHARING

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51780 )

Change subject: soc/amd/cezanne: Implement PROVIDES_ROM_SHARING
......................................................................

soc/amd/cezanne: Implement PROVIDES_ROM_SHARING

BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same

Signed-off-by: Raul E Rangel 
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/early_fch.c
2 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 5e0e1a6..9a108c9 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -30,6 +30,7 @@
    select PARALLEL_MP
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_0
+	select PROVIDES_ROM_SHARING
    select RESET_VECTOR_IN_RAM
    select RTC
    select SOC_AMD_COMMON
@@ -195,6 +196,14 @@
    int
    default 150

+config DISABLE_SPI_FLASH_ROM_SHARING
+	def_bool n
+	help
+	  Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
+	  which indicates a board level ROM transaction request. This
+	  removes arbitration with board and assumes the chipset controls
+	  the SPI flash bus entirely.
+
 menu "PSP Configuration Options"

config AMD_FWM_POSITION_INDEX
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index b00f49d..4e7d84d 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -60,6 +60,9 @@
    fch_print_pmxc0_status();
    i2c_soc_early_init();

+	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+		lpc_disable_spi_rom_sharing();
+
    if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
    	espi_setup();
    	espi_configure_decodes();