[S] Change in coreboot[master]: mb/google/octopus/variants/phaser: Implement variant_memory_sku()
Attention is currently required from: Jamie Chen, Derek Huang, Marco Chen, Eric Lai.
Stanley Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69925 )
Change subject: mb/google/octopus/variants/phaser: Implement variant_memory_sku() ......................................................................
Patch Set 3:
(17 comments)
File src/mainboard/google/octopus/variants/phaser/memory.c:
https://review.coreboot.org/c/coreboot/+/69925/comment/ce0080b9_39a2dd3b PS1, Line 24: size_t rt;
please, no spaces at the start of a line […]
Done
https://review.coreboot.org/c/coreboot/+/69925/comment/0f7ba7b1_cf7c5968 PS1, Line 24: size_t rt;
code indent should use tabs where possible […]
Done
https://review.coreboot.org/c/coreboot/+/69925/comment/774522ad_c1761ac5 PS1, Line 25: gpio_t pads[] = {
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/1ccaf5f2_66de7928 PS1, Line 25: gpio_t pads[] = {
code indent should use tabs where possible […]
Done
https://review.coreboot.org/c/coreboot/+/69925/comment/ff85e8d2_05c9962b PS1, Line 26: [3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/480c1d63_9369d1b4 PS1, Line 26: [3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/88e999e3_aeaafd70 PS1, Line 27: [1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/5a04a30a_1f8717d4 PS1, Line 27: [1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/703c7f4f_251f6073 PS1, Line 28: };
code indent should use tabs where possible […]
Done
https://review.coreboot.org/c/coreboot/+/69925/comment/0a8b6510_a5aac0b9 PS1, Line 28: };
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/1c44a30a_0f2a0dcf PS1, Line 30: rt = gpio_base2_value(pads, ARRAY_SIZE(pads));
code indent should use tabs where possible […]
Done
https://review.coreboot.org/c/coreboot/+/69925/comment/d498c7ae_b7de7b84 PS1, Line 30: rt = gpio_base2_value(pads, ARRAY_SIZE(pads));
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/3d92eee3_d2fff530 PS1, Line 31: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1
code indent should use tabs where possible […]
Done
https://review.coreboot.org/c/coreboot/+/69925/comment/ba09624f_4ab74f14 PS1, Line 31: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1
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Done
https://review.coreboot.org/c/coreboot/+/69925/comment/6e6eeb94_5603b778 PS1, Line 32: }
adding a line without newline at end of file […]
Done
File src/mainboard/google/octopus/variants/phaser/memory.c:
https://review.coreboot.org/c/coreboot/+/69925/comment/b3a4de66_1007570d PS2, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2017 Intel Corp. : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/google/octopus/variants/phaser/memory.c:
https://review.coreboot.org/c/coreboot/+/69925/comment/ac66325d_4f728b4a PS3, Line 18: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1
agree to add board id check to override memory ID for specific board id
Thanks for the suggestion. But there don`t have specific board_id define for ram_id=3 case. All board id is the same with MP shipping unit.
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Stanley Wu (Code Review)