Change in ...coreboot[master]: mb/ocp/monolake: fix for booting issues + tmp and ipmi support
Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31435
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
mb/ocp/monolake: fix for booting issues + tmp and ipmi support
This change brings monolake platform to sane state when it actually boots.
First of all - we experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec - helped and systems started to boot properly.
Secondly, changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable
Also I changed the length of SMBIOS type 38 entry. Subtracting 2 of it was effectively cutting information about register spacing, don't know why was it there on the first place.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/arch/x86/smbios.c M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 6 files changed, 172 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c0545ce..69be77d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -642,7 +642,7 @@ memset(t, 0, sizeof(struct smbios_type38)); t->type = SMBIOS_IPMI_DEVICE_INFORMATION; t->handle = *handle; - t->length = len - 2; + t->length = len; t->interface_type = interface_type; t->ipmi_rev = ipmi_rev; t->i2c_slave_addr = i2c_addr; diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 76ecb48..70b01c3 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,8 @@ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1
config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c2..2d91b73 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..e59bb32 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ { #include "acpi/platform.asl"
+ Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
@@ -290,5 +293,97 @@ } }
+ Scope (_SB.PCI0.LPC0) + { + Device(SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, _SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, _SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, _SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, _SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, _SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, _SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device(SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index f1a3a20..eacb577 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -14,18 +14,56 @@ * GNU General Public License for more details. */
+#include <console/console.h> #include <device/device.h> +#include <smbios.h> + #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif
+#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + +// static const unsigned char ipmi_command[] = {}; /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif
+ printk(BIOS_INFO, "mainboard_enable() called\n"); + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index cf52c01..4784dff 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,11 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <cpu/x86/msr.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h>
/** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +29,30 @@ */ void early_mainboard_romstage_entry(void) { + /* + * Sometimes the system boots in an invalid state, where random values + * have been written to MSRs and then the MSRs are locked. + * Seems to always happen on warm reset. + * + * Power cycling or a board_reset() isn't sufficient in this case, so + * issue a full_reset() to "fix" this issue. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if (msr.lo & 1) { + console_init(); + printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); + full_reset(); + }
+ pci_write_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, + 0x0c0681); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC, + 0xfc0201); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN4_DEC, + 0xfc0601); }
/** @@ -33,7 +61,6 @@ */ void late_mainboard_romstage_entry(void) { - }
/** @@ -41,5 +68,4 @@ */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - }
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 1:
(5 comments)
Please split the commit into smaller ones: One for SMBIOS and one for the monolake.
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/Kconfig File src/mainboard/ocp/monolake/Kconfig:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/Kconfig@1... PS1, Line 15: select MAINBOARD_HAS_TPM1 why not select the superio, too ? select SUPERIO_ITE_IT8528E why not disable the integrated soc uart ? config INTEGRATED_UART def_bool n
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl File src/mainboard/ocp/monolake/dsdt.asl:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 30: Name (IDTP, 0x0CA2) where are those comming from ? Is that something that can be configured in the superio ?
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 298: Device(SPMI) Device (
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 354: Device(SYSR) Device (
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/romstage.... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/romstage.... PS1, Line 47: pci_write_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); already done in soc code if CONFIG_INTEGRATED_UART==n
Łukasz Siudut has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 1:
(3 comments)
Sure! I may need a while to figure out how to do it properly though :). Thanks!
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl File src/mainboard/ocp/monolake/dsdt.asl:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 30: Name (IDTP, 0x0CA2)
where are those comming from ? […]
Those are standard ports for IPMI, Especially 0xca2. 0xca6 is upper boundary that I took from original DSDT.
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 298: Device(SPMI)
Device (
Ack
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 354: Device(SYSR)
Device (
Ack
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31435/1/src/arch/x86/smbios.c File src/arch/x86/smbios.c:
https://review.coreboot.org/#/c/31435/1/src/arch/x86/smbios.c@645 PS1, Line 645: t->length = len; The code here is a little odd. Each table has to be followed by two null bytes. So the `t->length` has to be two less than the number of bytes zeroed and reserved (`*current +=` below).
For other tables this is done by having two extra bytes at the end of the struct declaration (`u8 eos[2]`). It's an odd pattern, but might be worth to align this one here to avoid more confusion.
And please split the SMBIOS change out into a separate commit.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31435/1/src/arch/x86/smbios.c File src/arch/x86/smbios.c:
https://review.coreboot.org/#/c/31435/1/src/arch/x86/smbios.c@645 PS1, Line 645: t->length = len;
The code here is a little odd. Each table has to be followed […]
That's my bad. The type38 table was added in 2012 and I didn't verify that it contains eos[2] when adding the generator function in change #25386 .
Łukasz Siudut has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/Kconfig File src/mainboard/ocp/monolake/Kconfig:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/Kconfig@1... PS1, Line 15: select MAINBOARD_HAS_TPM1
why not select the superio, too ? […]
Regarding SUPERIO_ITE_IT8528E - I didn't select it deliberately as I'm not certain if the server even have the chip :).
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31435
to look at the new patch set (#2).
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
mb/ocp/monolake: fix for booting issues + tmp and ipmi support
This change brings monolake platform to sane state when it actually boots.
First of all - we experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec - helped and systems started to boot properly.
Secondly, changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable
Also I changed the length of SMBIOS type 38 entry. Subtracting 2 of it was effectively cutting information about register spacing, don't know why was it there on the first place.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/arch/x86/smbios.c M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 6 files changed, 172 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/2
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31435
to look at the new patch set (#3).
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
mb/ocp/monolake: fix for booting issues + tmp and ipmi support
This change brings monolake platform to sane state when it actually boots.
First of all - we experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec - helped and systems started to boot properly.
Secondly, changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable
Also I changed the length of SMBIOS type 38 entry. Subtracting 2 of it was effectively cutting information about register spacing, don't know why was it there on the first place.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 5 files changed, 173 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/3
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31435
to look at the new patch set (#4).
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
mb/ocp/monolake: fix for booting issues + tmp and ipmi support
This change brings monolake platform to sane state when it actually boots.
First of all - we experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec - helped and systems started to boot properly.
Secondly, changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable
Also I changed the length of SMBIOS type 38 entry. Subtracting 2 of it was effectively cutting information about register spacing, don't know why was it there on the first place.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 5 files changed, 173 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/4
Łukasz Siudut has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 4:
Ok, I addressed all the comments + rolled back smbios changes, will push different PR for that. Also just tested it and things are looking good. Thanks for the review!
FWIW working on that was tons of fun.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG@13 PS4, Line 13: 817994c1bec Please add the commit message summary in () behind the hash.
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG@19 PS4, Line 19: - introduced DSDT and SMBIOS entries for IPMI to make it detectable Please put all of this in separate commits.
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG@23 PS4, Line 23: why was it there on the first place. This can be removed now, can it?
Łukasz Siudut has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG@13 PS4, Line 13: 817994c1bec
Please add the commit message summary in () behind the hash.
Ack
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG@19 PS4, Line 19: - introduced DSDT and SMBIOS entries for IPMI to make it detectable
Please put all of this in separate commits.
Up, up to this descent? When you've been mentioning removing SMBIOS changes I actually though that you are referring to length change in smbios.c. No problem though.
https://review.coreboot.org/#/c/31435/4//COMMIT_MSG@23 PS4, Line 23: why was it there on the first place.
This can be removed now, can it?
Ack
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31435
to look at the new patch set (#5).
Change subject: mb/ocp/monolake: fix for booting issues ......................................................................
mb/ocp/monolake: fix for booting issues
We experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage: Workaround broken platform state) - helped and systems started to boot properly.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 2 files changed, 18 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/5
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31435
to look at the new patch set (#6).
Change subject: mb/ocp/monolake: fix for booting issues ......................................................................
mb/ocp/monolake: fix for booting issues
We experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage: Workaround broken platform state) - helped and systems started to boot properly.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/6
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues ......................................................................
Patch Set 6: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Thank you for addressing the comments.
https://review.coreboot.org/#/c/31435/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31435/6//COMMIT_MSG@7 PS6, Line 7: mb/ocp/monolake: fix for booting issues Last nit: Please use a statement by using a verb in imperative mood:
mb/ocp/monolake: Fix booting issues
Patrick Georgi has uploaded a new patch set (#7) to the change originally created by Łukasz Siudut. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: Fix booting issues ......................................................................
mb/ocp/monolake: Fix booting issues
We experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage: Workaround broken platform state) - helped and systems started to boot properly.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/7
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: Fix booting issues ......................................................................
mb/ocp/monolake: Fix booting issues
We experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage: Workaround broken platform state) - helped and systems started to boot properly.
Signed-off-by: Lukasz Siudut lsiudut@fb.com Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab Reviewed-on: https://review.coreboot.org/c/31435 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 17 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index cf52c01..2bb50f0 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,9 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <cpu/x86/msr.h> +#include <cf9_reset.h> +#include <console/console.h>
/** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +27,20 @@ */ void early_mainboard_romstage_entry(void) { - + /* + * Sometimes the system boots in an invalid state, where random values + * have been written to MSRs and then the MSRs are locked. + * Seems to always happen on warm reset. + * + * Power cycling or a board_reset() isn't sufficient in this case, so + * issue a full_reset() to "fix" this issue. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if (msr.lo & 1) { + console_init(); + printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); + full_reset(); + } }
/**
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Nico Huber (Code Review) -
Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)
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Łukasz Siudut (Code Review)