Hello Rob Barnes,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/43351
to review the following change.
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
soc/amd/picasso: supply smbios type 17
Extract dimm info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build smbios type 17 tables .
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c D src/vendorcode/amd/fsp/picasso/dmi_info.h 3 files changed, 201 insertions(+), 198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43351/1
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 593d17b..8b03d59 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -78,6 +78,7 @@ ramstage-y += config.c ramstage-y += update_microcode.c ramstage-y += graphics.c +ramstage-y += dmi.c
smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c new file mode 100644 index 0000000..c597c0a --- /dev/null +++ b/src/soc/amd/picasso/dmi.c @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/** + * This code was adapted from src/soc/amd/common/block/pi/amd_late_init.c + */ + +#include <fsp/util.h> +#include <memory_info.h> +#include <console/console.h> +#include <cbmem.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <bootstate.h> +#include <lib.h> +#include <dimm_info_util.h> +#include <vendorcode/amd/fsp/picasso/dmi_info.h> + +/** + * Populate dimm_info using AGESA TYPE17_DMI_INFO. + */ +static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17, + struct dimm_info *dimm) +{ + hexstrtobin(dmi17->SerialNumber, dimm->serial, sizeof(dimm->serial)); + + dimm->dimm_size = + smbios_memory_size_to_mib(dmi17->MemorySize, dmi17->ExtSize); + + dimm->ddr_type = dmi17->MemoryType; + + dimm->ddr_frequency = dmi17->Speed; + + dimm->rank_per_dimm = dmi17->Attributes; + + dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); + + dimm->bus_width = + smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + + dimm->mod_id = dmi17->ManufacturerIdCode; + + dimm->bank_locator = 0; + + strncpy((char *)dimm->module_part_number, dmi17->PartNumber, + sizeof(dimm->module_part_number) - 1); +} + +static void print_dimm_info(const struct dimm_info *dimm) +{ + printk(BIOS_DEBUG, + "CBMEM_ID_MEMINFO:\n" + " dimm_size: %u\n" + " ddr_type: 0x%hx\n" + " ddr_frequency: %hu\n" + " rank_per_dimm: %hhu\n" + " channel_num: %hhu\n" + " dimm_num: %hhu\n" + " bank_locator: %hhu\n" + " mod_id: %hx\n" + " mod_type: 0x%hhx\n" + " bus_width: %hhu\n" + " serial: %02hhx%02hhx%02hhx%02hhx\n" + " module_part_number(%zu): %s\n", + dimm->dimm_size, + dimm->ddr_type, + dimm->ddr_frequency, + dimm->rank_per_dimm, + dimm->channel_num, + dimm->dimm_num, + dimm->bank_locator, + dimm->mod_id, + dimm->mod_type, + dimm->bus_width, + dimm->serial[0], + dimm->serial[1], + dimm->serial[2], + dimm->serial[3], + strlen((const char *)dimm->module_part_number), + (char *)dimm->module_part_number); +} + +static void print_dmi_info(const TYPE17_DMI_INFO *dmi17) +{ + printk(BIOS_DEBUG, + "AGESA TYPE 17 DMI INFO:\n" + " Handle: %hu\n" + " TotalWidth: %hu\n" + " DataWidth: %hu\n" + " MemorySize: %hu\n" + " DeviceSet: %hhu\n" + " Speed: %hu\n" + " ManufacturerIdCode: %llx\n" + " Attributes: %hhu\n" + " ExtSize: %u\n" + " ConfigSpeed: %hu\n" + " MemoryType: 0x%x\n" + " FormFactor: 0x%x\n" + " DeviceLocator: %8s\n" + " BankLocator: %10s\n" + " SerialNumber(%zu): %9s\n" + " PartNumber(%zu): %19s\n", + dmi17->Handle, + dmi17->TotalWidth, + dmi17->DataWidth, + dmi17->MemorySize, + dmi17->DeviceSet, + dmi17->Speed, + dmi17->ManufacturerIdCode, + dmi17->Attributes, + dmi17->ExtSize, + dmi17->ConfigSpeed, + dmi17->MemoryType, + dmi17->FormFactor, + dmi17->DeviceLocator, + dmi17->BankLocator, + strlen((const char *)dmi17->SerialNumber), + dmi17->SerialNumber, + strlen((const char *)dmi17->PartNumber), + dmi17->PartNumber); +} + +/** + * Marshalls dimm info from AMD_FSP_DMI_HOB into CBMEM_ID_MEMINFO + */ +static void prepare_dmi_17(void *unused) +{ + const DMI_INFO *dmi_table; + const TYPE17_DMI_INFO *type17_dmi_info; + struct memory_info *mem_info; + struct dimm_info *dimm_info; + char cbi_part_number[DIMM_INFO_PART_NUMBER_SIZE]; + bool use_cbi_part_number = false; + int dimm_cnt = 0; + size_t amd_fsp_dmi_hob_size; + const EFI_GUID amd_fsp_dmi_hob_guid = AMD_FSP_DMI_HOB_GUID; + + printk(BIOS_DEBUG, "Saving dimm info for smbios type 17\n"); + + /* Allocate meminfo in cbmem. */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + if (!mem_info) { + printk(BIOS_ERR, "Failed to add memory info to CBMEM.\n"); + return; + } + memset(mem_info, 0, sizeof(struct memory_info)); + + /* Locate the memory info HOB. */ + dmi_table = fsp_find_extension_hob_by_guid( + (const uint8_t *)&amd_fsp_dmi_hob_guid, &amd_fsp_dmi_hob_size); + + if (dmi_table == NULL || amd_fsp_dmi_hob_size == 0) { + printk(BIOS_ERR, "AMD_FSP_DMI_HOB not found\n"); + return; + } + printk(BIOS_DEBUG, "AMD_FSP_DMI_HOB found\n"); + + /* Prefer DRAM part number from CBI. */ + if (google_chromeec_cbi_get_dram_part_num( + cbi_part_number, sizeof(cbi_part_number)) != 0) { + printk(BIOS_ERR, "Could not obtain DRAM part number from CBI\n"); + use_cbi_part_number = false; + } else { + use_cbi_part_number = true; + } + + for (int channel = 0; channel < MAX_CHANNELS_PER_SOCKET; channel++) { + for (int dimm = 0; dimm < MAX_DIMMS_PER_CHANNEL; dimm++) { + type17_dmi_info = &dmi_table->T17[0][channel][dimm]; + /* DIMMS that are present will have a non-zero + handle. */ + if (type17_dmi_info->Handle == 0) + continue; + print_dmi_info(type17_dmi_info); + dimm_info = &mem_info->dimm[dimm_cnt]; + dimm_info->channel_num = channel; + dimm_info->dimm_num = channel; + transfer_memory_info(type17_dmi_info, dimm_info); + if (use_cbi_part_number) { + /* mem_info is memset to 0 above, so it's + safe to assume module_part_number will be + null terminated */ + strncpy((char *)dimm_info->module_part_number, + cbi_part_number, + sizeof(dimm_info->module_part_number) + - 1); + } + print_dimm_info(dimm_info); + dimm_cnt++; + } + } + mem_info->dimm_cnt = dimm_cnt; +} + +// AMD_FSP_DMI_HOB is initialized very late, +// so check it just in time for writing tables. +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, prepare_dmi_17, NULL); diff --git a/src/vendorcode/amd/fsp/picasso/dmi_info.h b/src/vendorcode/amd/fsp/picasso/dmi_info.h deleted file mode 100644 index adab2f9..0000000 --- a/src/vendorcode/amd/fsp/picasso/dmi_info.h +++ /dev/null @@ -1,198 +0,0 @@ - /***************************************************************************** - * - * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/** - * This code was copied from src/vendorcode/amd/pi/00670F00/AGESA.h - */ - -#define AMD_FSP_DMI_HOB_GUID {0x4118FC0E, 0x353D, 0x4726, { 0x97, 0xC0, 0x53, 0xCD, 0x92, 0xB6, 0x49, 0x25}} - -// Our ACPI HOB max payload, accounting for the size of the HOB header as well as the information structure -#define HOB_MAX_SIZE 0xFFF8 -#define HOB_GUID_EXTENSION_SIZE (HOB_MAX_SIZE - sizeof (EFI_HOB_GUID_TYPE)) - -#define MAX_SOCKETS_SUPPORTED 1 ///< Max number of sockets in system -#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets -#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) - -/// DMI Type 16 offset 04h - Location -typedef enum { - OtherLocation = 0x01, ///< Assign 01 to Other - UnknownLocation, ///< Assign 02 to Unknown - SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard - IsaAddonCard, ///< Assign 04 to ISA add-on card - EisaAddonCard, ///< Assign 05 to EISA add-on card - PciAddonCard, ///< Assign 06 to PCI add-on card - McaAddonCard, ///< Assign 07 to MCA add-on card - PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card - ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card - NuBus, ///< Assign 0A to NuBus - Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card - Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card - Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card - Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card -} DMI_T16_LOCATION; - -/// DMI Type 16 offset 05h - Memory Error Correction -typedef enum { - OtherUse = 0x01, ///< Assign 01 to Other - UnknownUse, ///< Assign 02 to Unknown - SystemMemory, ///< Assign 03 to system memory - VideoMemory, ///< Assign 04 to video memory - FlashMemory, ///< Assign 05 to flash memory - NonvolatileRam, ///< Assign 06 to non-volatile RAM - CacheMemory ///< Assign 07 to cache memory -} DMI_T16_USE; - -/// DMI Type 16 offset 07h - Maximum Capacity -typedef enum { - Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other - Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown - Dmi16NoneErrCorrection, ///< Assign 03 to None - Dmi16Parity, ///< Assign 04 to parity - Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC - Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC - Dmi16Crc ///< Assign 07 to CRC -} DMI_T16_ERROR_CORRECTION; - -/// DMI Type 16 - Physical Memory Array -typedef struct { - OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, - ///< whether on the system board or an add-in board. - OUT DMI_T16_USE Use; ///< Identifies the function for which the array - ///< is used. - OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or - ///< detection method supported by this memory array. - OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available - ///< for memory devices in this array. -} TYPE16_DMI_INFO; - -/// DMI Type 17 offset 0Eh - Form Factor -typedef enum { - OtherFormFactor = 0x01, ///< Assign 01 to Other - UnknowFormFactor, ///< Assign 02 to Unknown - SimmFormFactor, ///< Assign 03 to SIMM - SipFormFactor, ///< Assign 04 to SIP - ChipFormFactor, ///< Assign 05 to Chip - DipFormFactor, ///< Assign 06 to DIP - ZipFormFactor, ///< Assign 07 to ZIP - ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card - DimmFormFactorFormFactor, ///< Assign 09 to DIMM - TsopFormFactor, ///< Assign 10 to TSOP - RowOfChipsFormFactor, ///< Assign 11 to Row of chips - RimmFormFactor, ///< Assign 12 to RIMM - SodimmFormFactor, ///< Assign 13 to SODIMM - SrimmFormFactor, ///< Assign 14 to SRIMM - FbDimmFormFactor ///< Assign 15 to FB-DIMM -} DMI_T17_FORM_FACTOR; - -/// DMI Type 17 offset 12h - Memory Type -typedef enum { - OtherMemType = 0x01, ///< Assign 01 to Other - UnknownMemType, ///< Assign 02 to Unknown - DramMemType, ///< Assign 03 to DRAM - EdramMemType, ///< Assign 04 to EDRAM - VramMemType, ///< Assign 05 to VRAM - SramMemType, ///< Assign 06 to SRAM - RamMemType, ///< Assign 07 to RAM - RomMemType, ///< Assign 08 to ROM - FlashMemType, ///< Assign 09 to Flash - EepromMemType, ///< Assign 10 to EEPROM - FepromMemType, ///< Assign 11 to FEPROM - EpromMemType, ///< Assign 12 to EPROM - CdramMemType, ///< Assign 13 to CDRAM - ThreeDramMemType, ///< Assign 14 to 3DRAM - SdramMemType, ///< Assign 15 to SDRAM - SgramMemType, ///< Assign 16 to SGRAM - RdramMemType, ///< Assign 17 to RDRAM - DdrMemType, ///< Assign 18 to DDR - Ddr2MemType, ///< Assign 19 to DDR2 - Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM - Ddr3MemType = 0x18, ///< Assign 24 to DDR3 - Fbd2MemType, ///< Assign 25 to FBD2 - Ddr4MemType, ///< Assign 26 to DDR4 - LpDdrMemType, ///< Assign 27 to LPDDR - LpDdr2MemType, ///< Assign 28 to LPDDR2 - LpDdr3MemType, ///< Assign 29 to LPDDR3 - LpDdr4MemType, ///< Assign 30 to LPDDR4 -} DMI_T17_MEMORY_TYPE; - -/// DMI Type 17 offset 13h - Type Detail -typedef struct { - OUT UINT16 Reserved1:1; ///< Reserved - OUT UINT16 Other:1; ///< Other - OUT UINT16 Unknown:1; ///< Unknown - OUT UINT16 FastPaged:1; ///< Fast-Paged - OUT UINT16 StaticColumn:1; ///< Static column - OUT UINT16 PseudoStatic:1; ///< Pseudo-static - OUT UINT16 Rambus:1; ///< RAMBUS - OUT UINT16 Synchronous:1; ///< Synchronous - OUT UINT16 Cmos:1; ///< CMOS - OUT UINT16 Edo:1; ///< EDO - OUT UINT16 WindowDram:1; ///< Window DRAM - OUT UINT16 CacheDram:1; ///< Cache Dram - OUT UINT16 NonVolatile:1; ///< Non-volatile - OUT UINT16 Registered:1; ///< Registered (Buffered) - OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) - OUT UINT16 LRDIMM:1; ///< LRDIMM -} DMI_T17_TYPE_DETAIL; - -/// DMI Type 17 - Memory Device -typedef struct { - OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure - OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. - OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. - OUT UINT16 MemorySize; ///< The size of the memory device. - OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. - OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of - ///< Memory Devices that must be populated with all devices of - ///< the same type and size, and the set to which this device belongs. - OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - OUT CHAR8 BankLocator[13]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. - OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. - OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type - OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT32 _Reserved1_; - OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. - OUT CHAR8 SerialNumber[9]; ///< Serial Number. - OUT CHAR8 PartNumber[21]; ///< Part Number. - OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. - OUT UINT32 ExtSize; ///< Extended Size. - OUT UINT16 ConfigSpeed; ///< Configured memory clock speed - OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts - OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts - OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts - OUT UINT32 _Reserved2_; -} TYPE17_DMI_INFO; - -/// Collection of pointers to the DMI records -typedef struct { - OUT TYPE16_DMI_INFO T16; ///< Type 16 struc - OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc -} DMI_INFO;
Hello Patrick Georgi, Martin Roth, Rob Barnes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43351
to look at the new patch set (#2).
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
soc/amd/picasso: supply smbios type 17
Extract dimm info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build smbios type 17 tables .
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c 2 files changed, 201 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43351/2
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 2: Code-Review+1
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 2: Code-Review+2
Rob Barnes has uploaded a new patch set (#3) to the change originally created by Aaron Durbin. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
soc/amd/picasso: supply smbios type 17
Extract dimm info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build smbios type 17 tables .
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c 2 files changed, 204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43351/3
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 3: Code-Review+1
Change to exclude cbi call for mandolin.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c File src/soc/amd/picasso/dmi.c:
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 16: #if CONFIG(CHROMEOS) nit: I don't think we need to guard this.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 163: #if CONFIG(CHROMEOS) Use; if (CONFIG(CHROMEOS)) { }
instead of #if CONFIG(CHROMEOS)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 3:
(10 comments)
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@11 PS3, Line 11: from cbmem to build smbios type 17 tables . Please remove the space before the dot/period.
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@14 PS3, Line 14: TEST=dmidecode -t 17 Is boot time affected by this?
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c File src/soc/amd/picasso/dmi.c:
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@3... PS3, Line 33: smbios_memory_size_to_mib(dmi17->MemorySize, dmi17->ExtSize); Should fit in 96 characters?
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 139: int size_t
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 148: printk(BIOS_ERR, "Failed to add memory info to CBMEM.\n"); … DMI tables will be incomplete.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 158: printk(BIOS_ERR, "AMD_FSP_DMI_HOB not found\n"); … DMI table 17 won’t be populated.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 173: int unsigned int
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 174: int unsigned int
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 176: DIMMS DIMMs
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@2... PS3, Line 202: // so check it just in time for writing tables. 1. Should fit in one line. 2. Please use C89 comments in this file for consistency.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply smbios type 17 ......................................................................
Patch Set 3:
(7 comments)
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@7 PS3, Line 7: smbios SMBIOS
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@9 PS3, Line 9: dimm DRAM. I doubt that google/zork has DIMM slots.
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@11 PS3, Line 11: smbios SMBIOS
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c File src/soc/amd/picasso/dmi.c:
PS3: Name this file `smbios.c` instead?
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1 PS3, Line 1: /* : * This file is part of the coreboot project. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */ /* SPDX-License-Identifier: GPL-2.0-or-later */
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 173: int channel = 0 I'm not sure if we have any rule about for-loop variable declaration. I've usually seen those declared outside loops in coreboot.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 192: - 1 Move to the previous line?
Rob Barnes has uploaded a new patch set (#4) to the change originally created by Aaron Durbin. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c 2 files changed, 204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43351/4
Rob Barnes has uploaded a new patch set (#5) to the change originally created by Aaron Durbin. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c 2 files changed, 196 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43351/5
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 5:
(19 comments)
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@7 PS3, Line 7: smbios
SMBIOS
Done
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@9 PS3, Line 9: dimm
DRAM. I doubt that google/zork has DIMM slots.
Done
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@11 PS3, Line 11: smbios
SMBIOS
Done
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@11 PS3, Line 11: from cbmem to build smbios type 17 tables .
Please remove the space before the dot/period.
Done
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@14 PS3, Line 14: TEST=dmidecode -t 17
Is boot time affected by this?
I don't expect a significant impact, but it has not been measured.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c File src/soc/amd/picasso/dmi.c:
PS3:
Name this file `smbios. […]
I considered smbios.c, memory.c and dmi.c. I went with dmi.c because there are other smbios.c files in coreboot with different purposes. I'm open to changing it if there's a consensus.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1 PS3, Line 1: /* : * This file is part of the coreboot project. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 16: #if CONFIG(CHROMEOS)
nit: I don't think we need to guard this.
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@3... PS3, Line 33: smbios_memory_size_to_mib(dmi17->MemorySize, dmi17->ExtSize);
Should fit in 96 characters?
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 139: int
size_t
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 148: printk(BIOS_ERR, "Failed to add memory info to CBMEM.\n");
… DMI tables will be incomplete.
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 158: printk(BIOS_ERR, "AMD_FSP_DMI_HOB not found\n");
… DMI table 17 won’t be populated.
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 163: #if CONFIG(CHROMEOS)
Use; […]
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 173: int
unsigned int
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 173: int channel = 0
I'm not sure if we have any rule about for-loop variable declaration. […]
I see both. The style guide does not specify.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 174: int
unsigned int
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 176: DIMMS
DIMMs
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 192: - 1
Move to the previous line?
Done
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@2... PS3, Line 202: // so check it just in time for writing tables.
- Should fit in one line. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 5: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/43351/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43351/5//COMMIT_MSG@14 PS5, Line 14: dmidecode -t 17 Can you paste the boot logs showing the dumps, just curious.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43351/3//COMMIT_MSG@14 PS3, Line 14: TEST=dmidecode -t 17
I don't expect a significant impact, but it has not been measured.
If I'm interpreting cbmem -t correctly, the write tables phase increased from ~14 us to ~341 us.
https://review.coreboot.org/c/coreboot/+/43351/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43351/5//COMMIT_MSG@14 PS5, Line 14: dmidecode -t 17
Can you paste the boot logs showing the dumps, just curious.
localhost ~ # dmidecode -t 17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 2.8 present.
Handle 0x000A, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 1600 MT/s Manufacturer: Micron Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 1600 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown
Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-1-DIMM-1 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 1600 MT/s Manufacturer: Micron Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 1600 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c File src/soc/amd/picasso/dmi.c:
PS3:
I considered smbios.c, memory.c and dmi.c. I went with dmi.c because there are other smbios. […]
Reopen if there's consensus on renaming.
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 173: int channel = 0
I see both. The style guide does not specify.
Resolving.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 5: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c File src/soc/amd/picasso/dmi.c:
PS3:
Reopen if there's consensus on renaming.
Not a big deal. It's just that when I see "DMI" I think of Intel's Direct Media Interface, and get confused 😜
https://review.coreboot.org/c/coreboot/+/43351/3/src/soc/amd/picasso/dmi.c@1... PS3, Line 173: int channel = 0
Resolving.
Ack
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 5:
Rob - there is a merge conflict. You will have to rebase this so that it can be submitted.
Rob Barnes has uploaded a new patch set (#6) to the change originally created by Aaron Durbin. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c 2 files changed, 196 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43351/6
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 6:
Patch Set 5:
Rob - there is a merge conflict. You will have to rebase this so that it can be submitted.
Done
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
Patch Set 6: Code-Review+2
Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43351 )
Change subject: soc/amd/picasso: supply SMBIOS type 17 ......................................................................
soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes robbarnes@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/dmi.c 2 files changed, 196 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 823d933..b3af1fd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -79,6 +79,7 @@ ramstage-y += graphics.c ramstage-y += pcie_gpp.c ramstage-y += xhci.c +ramstage-y += dmi.c
smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c new file mode 100644 index 0000000..860778d --- /dev/null +++ b/src/soc/amd/picasso/dmi.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/** + * This code was adapted from src/soc/amd/common/block/pi/amd_late_init.c + */ + +#include <fsp/util.h> +#include <memory_info.h> +#include <console/console.h> +#include <cbmem.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <bootstate.h> +#include <lib.h> +#include <dimm_info_util.h> +#include <vendorcode/amd/fsp/picasso/dmi_info.h> + +/** + * Populate dimm_info using AGESA TYPE17_DMI_INFO. + */ +static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17, + struct dimm_info *dimm) +{ + hexstrtobin(dmi17->SerialNumber, dimm->serial, sizeof(dimm->serial)); + + dimm->dimm_size = smbios_memory_size_to_mib(dmi17->MemorySize, dmi17->ExtSize); + + dimm->ddr_type = dmi17->MemoryType; + + dimm->ddr_frequency = dmi17->Speed; + + dimm->rank_per_dimm = dmi17->Attributes; + + dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); + + dimm->bus_width = + smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + + dimm->mod_id = dmi17->ManufacturerIdCode; + + dimm->bank_locator = 0; + + strncpy((char *)dimm->module_part_number, dmi17->PartNumber, + sizeof(dimm->module_part_number) - 1); +} + +static void print_dimm_info(const struct dimm_info *dimm) +{ + printk(BIOS_DEBUG, + "CBMEM_ID_MEMINFO:\n" + " dimm_size: %u\n" + " ddr_type: 0x%hx\n" + " ddr_frequency: %hu\n" + " rank_per_dimm: %hhu\n" + " channel_num: %hhu\n" + " dimm_num: %hhu\n" + " bank_locator: %hhu\n" + " mod_id: %hx\n" + " mod_type: 0x%hhx\n" + " bus_width: %hhu\n" + " serial: %02hhx%02hhx%02hhx%02hhx\n" + " module_part_number(%zu): %s\n", + dimm->dimm_size, + dimm->ddr_type, + dimm->ddr_frequency, + dimm->rank_per_dimm, + dimm->channel_num, + dimm->dimm_num, + dimm->bank_locator, + dimm->mod_id, + dimm->mod_type, + dimm->bus_width, + dimm->serial[0], + dimm->serial[1], + dimm->serial[2], + dimm->serial[3], + strlen((const char *)dimm->module_part_number), + (char *)dimm->module_part_number); +} + +static void print_dmi_info(const TYPE17_DMI_INFO *dmi17) +{ + printk(BIOS_DEBUG, + "AGESA TYPE 17 DMI INFO:\n" + " Handle: %hu\n" + " TotalWidth: %hu\n" + " DataWidth: %hu\n" + " MemorySize: %hu\n" + " DeviceSet: %hhu\n" + " Speed: %hu\n" + " ManufacturerIdCode: %llx\n" + " Attributes: %hhu\n" + " ExtSize: %u\n" + " ConfigSpeed: %hu\n" + " MemoryType: 0x%x\n" + " FormFactor: 0x%x\n" + " DeviceLocator: %8s\n" + " BankLocator: %10s\n" + " SerialNumber(%zu): %9s\n" + " PartNumber(%zu): %19s\n", + dmi17->Handle, + dmi17->TotalWidth, + dmi17->DataWidth, + dmi17->MemorySize, + dmi17->DeviceSet, + dmi17->Speed, + dmi17->ManufacturerIdCode, + dmi17->Attributes, + dmi17->ExtSize, + dmi17->ConfigSpeed, + dmi17->MemoryType, + dmi17->FormFactor, + dmi17->DeviceLocator, + dmi17->BankLocator, + strlen((const char *)dmi17->SerialNumber), + dmi17->SerialNumber, + strlen((const char *)dmi17->PartNumber), + dmi17->PartNumber); +} + +/** + * Marshalls dimm info from AMD_FSP_DMI_HOB into CBMEM_ID_MEMINFO + */ +static void prepare_dmi_17(void *unused) +{ + const DMI_INFO *dmi_table; + const TYPE17_DMI_INFO *type17_dmi_info; + struct memory_info *mem_info; + struct dimm_info *dimm_info; + char cbi_part_number[DIMM_INFO_PART_NUMBER_SIZE]; + bool use_cbi_part_number = false; + size_t dimm_cnt = 0; + size_t amd_fsp_dmi_hob_size; + const EFI_GUID amd_fsp_dmi_hob_guid = AMD_FSP_DMI_HOB_GUID; + + printk(BIOS_DEBUG, "Saving dimm info for smbios type 17\n"); + + /* Allocate meminfo in cbmem. */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + if (!mem_info) { + printk(BIOS_ERR, + "Failed to add memory info to CBMEM, DMI tables will be incomplete\n"); + return; + } + memset(mem_info, 0, sizeof(struct memory_info)); + + /* Locate the memory info HOB. */ + dmi_table = fsp_find_extension_hob_by_guid( + (const uint8_t *)&amd_fsp_dmi_hob_guid, &amd_fsp_dmi_hob_size); + + if (dmi_table == NULL || amd_fsp_dmi_hob_size == 0) { + printk(BIOS_ERR, + "AMD_FSP_DMI_HOB not found, DMI table 17 will be incomplete\n"); + return; + } + printk(BIOS_DEBUG, "AMD_FSP_DMI_HOB found\n"); + + if (CONFIG(CHROMEOS)) { + /* Prefer DRAM part number from CBI. */ + if (google_chromeec_cbi_get_dram_part_num( + cbi_part_number, sizeof(cbi_part_number)) == 0) { + use_cbi_part_number = true; + } else { + printk(BIOS_ERR, "Could not obtain DRAM part number from CBI\n"); + } + } + + for (unsigned int channel = 0; channel < MAX_CHANNELS_PER_SOCKET; channel++) { + for (unsigned int dimm = 0; dimm < MAX_DIMMS_PER_CHANNEL; dimm++) { + type17_dmi_info = &dmi_table->T17[0][channel][dimm]; + /* DIMMs that are present will have a non-zero + handle. */ + if (type17_dmi_info->Handle == 0) + continue; + print_dmi_info(type17_dmi_info); + dimm_info = &mem_info->dimm[dimm_cnt]; + dimm_info->channel_num = channel; + dimm_info->dimm_num = channel; + transfer_memory_info(type17_dmi_info, dimm_info); + if (use_cbi_part_number) { + /* mem_info is memset to 0 above, so it's + safe to assume module_part_number will be + null terminated */ + strncpy((char *)dimm_info->module_part_number, cbi_part_number, + sizeof(dimm_info->module_part_number) - 1); + } + print_dimm_info(dimm_info); + dimm_cnt++; + } + } + mem_info->dimm_cnt = dimm_cnt; +} + +/* AMD_FSP_DMI_HOB is initialized very late, so check it just in time for writing tables. */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, prepare_dmi_17, NULL);