[S] Change in coreboot[main]: mb/asrock/z77_extreme4: Enable voltage rail adjustments

[Riku Viitanen (Code Review)]

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85795?usp=email )

Change subject: mb/asrock/z77_extreme4: Enable voltage rail adjustments
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mb/asrock/z77_extreme4: Enable voltage rail adjustments

This board has two Nuvoton NCT3933U current DAC chips on SMBus,
enabling firmware to adjust several voltage rails. The correct
registers and offsets were reverse engineered by adjusting voltages
in vendor firmware and observing what it wrote there.

Works with commit 7fa8a3aeeea4 (nb/sandybridge: Implement automatic
DRAM voltage setting) to enable firmware to set the DRAM voltage.

TEST=With few XMP and non-XMP modules. Monitored DRAM voltage on
test point VT10 (located near the SLI logo) with a multimeter.

Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51
Signed-off-by: Riku Viitanen 
---
M src/mainboard/asrock/z77_extreme4/Kconfig
M src/mainboard/asrock/z77_extreme4/Makefile.mk
A src/mainboard/asrock/z77_extreme4/romstage.c
3 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85795/1

diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig b/src/mainboard/asrock/z77_extreme4/Kconfig
index 4b31543..d5092c2 100644
--- a/src/mainboard/asrock/z77_extreme4/Kconfig
+++ b/src/mainboard/asrock/z77_extreme4/Kconfig
@@ -12,6 +12,7 @@
    select HAVE_OPTION_TABLE
    select INTEL_GMA_HAVE_VBT
    select INTEL_INT15
+	select MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE
    select MAINBOARD_HAS_LIBGFXINIT
    select NORTHBRIDGE_INTEL_SANDYBRIDGE
    select SERIRQ_CONTINUOUS_MODE
diff --git a/src/mainboard/asrock/z77_extreme4/Makefile.mk b/src/mainboard/asrock/z77_extreme4/Makefile.mk
index e4b6fbf..7e36e28 100644
--- a/src/mainboard/asrock/z77_extreme4/Makefile.mk
+++ b/src/mainboard/asrock/z77_extreme4/Makefile.mk
@@ -2,6 +2,7 @@

bootblock-y += gpio.c
 romstage-y += gpio.c
+romstage-y += romstage.c

ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 bootblock-y += early_init.c
diff --git a/src/mainboard/asrock/z77_extreme4/romstage.c b/src/mainboard/asrock/z77_extreme4/romstage.c
new file mode 100644
index 0000000..e0f0913
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/romstage.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <stdint.h>
+#include <console/console.h>
+#include <commonlib/bsd/helpers.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <device/smbus_host.h>
+
+struct nct3933u_ch {
+	uint8_t address;
+	uint8_t channel;
+	int voltage_default; /* in microvolts */
+	int voltage_step;    /* in microvolts */
+};
+
+struct nct3933u_ch cpu_pll = {0x14, 1, 1832000, 8200};
+struct nct3933u_ch vtt =     {0x14, 2, 1048000, 9313};
+struct nct3933u_ch pch =     {0x14, 3, 1059000, 9313};
+/*struct nct3933u_ch vrefca_a = {0x15, 1, ?, ?};*/
+/*struct nct3933u_ch vrefdq_a = {0x15, 2, ?, ?};*/
+struct nct3933u_ch dram =    {0x15, 3, 1600000, 5000};
+
+
+/* takes millivolts as input */
+static enum cb_err set_voltage(struct nct3933u_ch dac, int voltage) {
+	voltage *= 1000; /* Convert to microvolts */
+	int offset = (voltage - dac.voltage_default)/dac.voltage_step;
+
+	if ((offset > 127) || (offset < -127))
+		return CB_ERR;
+
+	/* Convert the offset to sign-magnitude format for NCT3933U */
+	offset = (ABS(offset) & 0x7f) | (offset & 0x80);
+
+	smbus_write_byte(dac.address, dac.channel, offset);
+
+	return CB_SUCCESS;
+}
+
+void mainboard_set_dram_voltage(int voltage) {
+	set_voltage(dram, voltage);
+}