[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
Attention is currently required from: Bora Guvendik, Subrata Banik, Zhixing Ma.
Zhixing Ma has posted comments on this change by Zhixing Ma. ( https://review.coreboot.org/c/coreboot/+/85960?usp=email )
Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85960/comment/00d7ce1d_2b9f3c4e?usp... : PS5, Line 16:
can you please add smbios data w/o and w/ this patch for easy review ? […]
Hi Subrata, Here is the dmidecode output with and without this patch, as well as a comparison to MTL platform (rex): without patch: ``` Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: Unknown ``` with patch: ``` Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: Other ``` on rex: ``` Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: A4 06 0A 00 FF FB EB BF Signature: Type 0, Family 6, Model 170, Stepping 4 Flags: ... Version: Genuine Intel(R) 0000 Voltage: 1.2 V External Clock: 100 MHz Max Speed: 4900 MHz Current Speed: 2700 MHz Status: Populated, Enabled Upgrade: Other ... ```
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Zhixing Ma (Code Review)