Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63672 )
Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ......................................................................
superio/ite/common: Add support for SuperIOs with 6 temperature reading registers
Some ITE SuperIOs such as IT8613E or IT8625E have 6 temperature reading registers, to which values can be read from any TMPINs or external sources. These SuperIOs have Temperature Source Select registers in bank 2 of EC space. Enable thermal monitoring on these SIOs by programming these registers.
Additionally, decouple temperature offset/min/max configuration from TMPIN mode configuration, since in these SIOs, TMPINs do not have to map directly to temperature reading registers (e.g. TMPIN1 can read to temperature reading register 3).
Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs.
Based on IT8613E "Preliminary Specification V0.3 (For E Version)" and IT8625E "Preliminary Specification V0.3 (For D Version)"
Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Signed-off-by: Michał Kopeć michal.kopec@3mdeb.com --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/it8613e/Kconfig 10 files changed, 126 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63672/1
diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index a713f34..f8d426d1 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -54,9 +54,9 @@ register "TMPIN1.mode" = "THERMAL_DIODE" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_PECI" - register "TMPIN3.offset" = "100" - register "TMPIN3.min" = "0" - register "TMPIN3.max" = "100" + register "TEMP3.offset" = "100" + register "TEMP3.min" = "0" + register "TEMP3.max" = "100"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan register "FAN1.smart.tmpin" = "3" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..d9eb149 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -53,7 +53,7 @@ device pci 1f.0 on # ISA bridge chip superio/ite/it8720f # Super I/O register "TMPIN1.mode" = "THERMAL_DIODE" - register "TMPIN1.offset" = "0" + register "TEMP1.offset" = "0" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..6880b85 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -102,7 +102,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN_ALL"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d7ddf9e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -72,7 +72,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33..d4bbbac 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -194,10 +194,10 @@ end chip superio/ite/it8786e register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "100" - register "TMPIN1.min" = "128" + register "TEMP1.offset" = "100" + register "TEMP1.min" = "128" register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN2.min" = "128" + register "TEMP2.min" = "128" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" register "ec.vin_mask" = "VIN_ALL" # FAN1 is CPU fan (on board) diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 36c1496..f1b7c74 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -48,4 +48,10 @@ Temperature can be read to any TMPIN from an external sensor via SST/PECI (instead of TMPIN3 only).
+config SUPERIO_ITE_ENV_CTRL_6_TEMPS + bool + help + Temperature can be read to 6 temperature reading registers from external + or physical inputs, selectable using TSS registers in Bank 2. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9149c58..854e39b 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -58,7 +58,7 @@ * into TMPINx register */ static void enable_tmpin(const u16 base, const u8 tmpin, - const struct ite_ec_thermal_config *const conf) + const struct ite_ec_tmpin_config *const conf) { u8 reg; u8 reg_extra; @@ -110,18 +110,59 @@
pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg);
- /* Set temperature offsets */ - if (conf->mode != THERMAL_RESISTOR) { - reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); - reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; - pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); - pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); +} + +static void ite_ec_select_bank(const u16 base, const u8 bank) +{ + uint8_t reg; + + reg = pnp_read_hwm5_index(base, ITE_EC_REG_SMI_MASK_3); + reg &= ~ITE_EC_BANK_SEL_MASK; + reg |= (bank << 5); + pnp_write_hwm5_index(base, ITE_EC_REG_SMI_MASK_3, reg); +} + +static int source_is_peci(enum ite_ec_thermal_source source) +{ + if (source >= THERMAL_SOURCE_PECI1 && source <= THERMAL_SOURCE_PECI5) + return 1; + + return 0; +} + +/* + * Configure temperature reading registers (offsets, limits, sources) + */ +static void enable_temp(const u16 base, const u8 temp, + const struct ite_ec_thermal_config *const conf) + +{ + u8 reg; + + if (CONFIG(SUPERIO_ITE_ENV_CTRL_6_TEMPS)) { + /* Set temperature sources */ + ite_ec_select_bank(base, 0x2); + reg = pnp_read_hwm5_index(base, ITE_EC_REG_TSS1(temp - 1)); + reg &= ~ITE_EC_REG_TSS1_MASK(temp - 1); + reg |= conf->source << ITE_EC_REG_TSS1_OFFSET(temp - 1); + pnp_write_hwm5_index(base, ITE_EC_REG_TSS1(temp - 1), reg); + ite_ec_select_bank(base, 0x0); + + /* Enable PECI if needed */ + if (source_is_peci(conf->source)) + enable_peci(base); }
+ /* Set temperature offsets */ + reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); + reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[temp - 1], conf->offset); + /* Set temperature limits */ u8 max = conf->max; - pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127); - pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT[temp - 1], max ? max : 127); + pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT[temp - 1], conf->min);
/* Enable the startup of monitoring operation */ reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION); @@ -286,6 +327,10 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]);
+ /* Configure temperature reading registers */ + for (i = 0; i < ITE_EC_TEMP_CNT; ++i) + enable_temp(base, i + 1, &conf->temp[i]); + /* Enable External Sensor SMBus Host if configured */ if (conf->smbus_en) { pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, @@ -315,7 +360,13 @@ * busy state. Therefore, check the status and terminate * processes if needed. */ - for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) - if (conf->tmpin[i].mode == THERMAL_PECI) - extemp_force_idle_status(base); + if (CONFIG(SUPERIO_ITE_ENV_CTRL_6_TEMPS)) { + for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) + if (conf->tmpin[i].mode == THERMAL_PECI) + extemp_force_idle_status(base); + } else { + for (i = 0; i < ITE_EC_TEMP_CNT; ++i) + if (source_is_peci(conf->temp[i].source)) + extemp_force_idle_status(base); + } } diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 5a31e7c..21e6cea 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -119,8 +119,9 @@ : (_p / 16); \ })
-#define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) -#define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) + +static const uint8_t ITE_EC_HIGH_TEMP_LIMIT[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 }; +static const uint8_t ITE_EC_LOW_TEMP_LIMIT[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
#define ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE 0x50 #define ITE_EC_ADC_TEMP_CHANNEL_ENABLE 0x51 @@ -131,8 +132,14 @@ #define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55 #define ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT (1 << 7)
-/* Matches length of ITE_EC_TMPIN_CNT */ -static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; +#define ITE_EC_REG_SMI_MASK_3 0x06 +#define ITE_EC_BANK_SEL_MASK 0x60 + +static const uint8_t ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 }; + +#define ITE_EC_REG_TSS1(x) (0x1D + ((x) / 2)) +#define ITE_EC_REG_TSS1_OFFSET(x) (((x) % 2) ? 4 : 0) +#define ITE_EC_REG_TSS1_MASK(x) (0xF << ITE_EC_REG_TSS1_OFFSET(x))
#define ITE_EC_BEEP_ENABLE 0x5C #define ITE_EC_TEMP_ADJUST_WRITE_ENABLE (1 << 7) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 2bb0780..54d9257 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -5,6 +5,12 @@
#define ITE_EC_TMPIN_CNT 3
+#if CONFIG(SUPERIO_ITE_ENV_CTRL_6_TEMPS) +#define ITE_EC_TEMP_CNT 6 +#else +#define ITE_EC_TEMP_CNT 3 +#endif + #if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CNT 5 #else @@ -12,15 +18,30 @@ #endif
/* Supported thermal mode on TMPINx */ -enum ite_ec_thermal_mode { +enum ite_ec_tmpin_mode { THERMAL_MODE_DISABLED = 0, THERMAL_DIODE, THERMAL_RESISTOR, THERMAL_PECI, };
+struct ite_ec_tmpin_config { + enum ite_ec_tmpin_mode mode; +}; + +enum ite_ec_thermal_source { + THERMAL_SOURCE_TMPIN1 = 0, + THERMAL_SOURCE_TMPIN2 = 1, + THERMAL_SOURCE_TMPIN3 = 2, + THERMAL_SOURCE_PECI1 = 4, + THERMAL_SOURCE_PECI2 = 5, + THERMAL_SOURCE_PECI3 = 6, + THERMAL_SOURCE_PECI4 = 7, + THERMAL_SOURCE_PECI5 = 8, +}; + struct ite_ec_thermal_config { - enum ite_ec_thermal_mode mode; + enum ite_ec_thermal_source source; /* Offset is used for diode sensors and PECI */ u8 offset; /* Limits */ @@ -78,7 +99,12 @@ /* * Enable temperature sensors in given mode. */ - struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT]; + struct ite_ec_tmpin_config tmpin[ITE_EC_TMPIN_CNT]; + + /* + * Configure temperature reading registers. + */ + struct ite_ec_thermal_config temp[ITE_EC_TEMP_CNT];
/* * Enable a FAN in given mode. @@ -105,6 +131,13 @@ #define TMPIN2 ec.tmpin[1] #define TMPIN3 ec.tmpin[2]
+#define TEMP1 ec.temp[0] +#define TEMP2 ec.temp[1] +#define TEMP3 ec.temp[2] +#define TEMP4 ec.temp[3] +#define TEMP5 ec.temp[4] +#define TEMP6 ec.temp[5] + #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2] diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index e6f01c4..9d5eb6a 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -8,4 +8,4 @@ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF - select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_6_TEMPS
-
Michał Kopeć (Code Review)