Change in coreboot[master]: soc/intel/alderlake: Disable RTD3 and D3 Cold for TCSS

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48696 )

Change subject: soc/intel/alderlake: Disable RTD3 and D3 Cold for TCSS
......................................................................

soc/intel/alderlake: Disable RTD3 and D3 Cold for TCSS

Signed-off-by: Meera Ravindranath 
Change-Id: Idd792eaf76f49be05060ac3f3ddb03336f3e6e06
---
M src/soc/intel/alderlake/acpi/tcss_dma.asl
M src/soc/intel/alderlake/acpi/tcss_pcierp.asl
M src/soc/intel/alderlake/acpi/tcss_xhci.asl
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/48696/1

diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl
index da2e8fe..ebbea69 100644
--- a/src/soc/intel/alderlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl
@@ -70,7 +70,7 @@
  * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE
  * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
  */
-Name (SD3C, 0)
+Name (SD3C, 1)

Method (_DSW, 3)
 {
diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index abca5d1..c0eeeb9 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -159,7 +159,7 @@
  */
 Method (D3CE, 0, Serialized)
 {
-	If (STAT == 0x0) {
+	If (STAT == 0x1) {
    	Return
    }

diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
index acbeb30..31a3454 100644
--- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
@@ -37,7 +37,7 @@
  * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE
  * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
  */
-Name (SD3C, 0)
+Name (SD3C, 1)

Method (_PR0)
 {