New patch to review for coreboot: 54510a7 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3576
-gerrit
commit 54510a73fb3904dc468130ec2ca4bbe86878f1cf Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Jul 1 11:21:53 2013 +0300
intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock.
Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/google/stout/Kconfig | 1 - src/mainboard/intel/emeraldlake2/Kconfig | 1 - src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/samsung/lumpy/Kconfig | 1 - src/mainboard/samsung/stumpy/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 8 ++++++++ src/northbridge/intel/sandybridge/bootblock.c | 26 ++++++++++++++++++++++++++ src/northbridge/intel/sandybridge/early_init.c | 2 -- 11 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index d41a9f5..be585c7 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 4bddc5f..f62d690 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 3081b5a..dbdb5fa 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index a15d933..a5b7962 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 20685f3..786e9a8 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select GFXUMA #select CHROMEOS select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index dafc959..97d8e5c 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index a169726..1c18ec2 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select MMCONF_SUPPORT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index fa7d03d..f4df8a9 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select MMCONF_SUPPORT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 3a65782..59b6187 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,11 +20,15 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX
config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX
if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -103,6 +107,10 @@ endif
if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
+config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/sandybridge/bootblock.c" + config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c new file mode 100644 index 0000000..1c1d492 --- /dev/null +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -0,0 +1,26 @@ +#include <arch/io.h> + +/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909..583385b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -49,8 +49,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
-
Kyösti Mälkki