Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
2 files changed, 35 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/1

diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 11fe44b..c017d79 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -14,7 +14,9 @@
 #include <soc/ramstage.h>
 #include <soc/pm.h>
 #include <soc/soc_util.h>
+#include <soc/pci_devs.h>
 #include <stdlib.h>
+#include <security/intel/txt/txt_platform.h>

/* C620 IOAPIC has 120 redirection entries */
 #define C620_IOAPIC_REDIR_ENTRIES		120
@@ -558,6 +560,38 @@
    DEV_FUNC_EXIT(dev);
 }

+union dpr_register txt_get_chipset_dpr(void)
+{
+	struct iiostack_resource info;
+	union dpr_register dpr;
+	const pci_devfn_t VTD = PCI_DEVFN(VTD_DEV, VTD_FUNC);
+	const struct device *dev = pcidev_path_on_root(VTD);
+
+	if (dev == NULL)
+		die("Unable to find VTD PCI DEV");
+
+	dpr.raw = pci_read_config32(dev, VTD_LTDPR);
+
+	get_iiostack_info(&info);
+	for (int s = 1; s < info.no_of_stacks; s++) {
+		uint8_t bus = info.res[s].BusBase;
+		dev = pcidev_path_on_bus(bus, VTD);
+
+		if (dev == NULL)
+			die("Unable to find VTD PCI DEV");
+
+		union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
+		if (memcmp(&dpr, &test_dpr, sizeof(dpr))) {
+			printk(BIOS_ERR, "LTDPR not the same on all IIO's");
+			/* TODO: Have the caller check this */
+			dpr.raw = 0;
+			return dpr;
+		}
+	}
+
+	return dpr;
+}
+
 struct pci_operations soc_pci_ops = {
    .set_subsystem = pci_dev_set_subsystem,
 };
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 965bb66..4d04105 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -70,6 +70,7 @@
 #define VTD_CAP_LOW			0x08
 #define VTD_CAP_HIGH			0x0C
 #define VTD_EXT_CAP_HIGH		0x14
+#define VTD_LTDPR			0x290

/* CPU Devices */
 #define CBDMA_DEV_NUM           0x04

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 5: Code-Review+1

(4 comments)

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
File src/soc/intel/xeon_sp/cpx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 571: die
Can something else be done instead of dying?

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 571: DEV
I'd use `dev` in lowercase (or `device`), and also indicate which stack this is on.

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 581: 			die("Unable to find VTD PCI DEV");
Same comments here

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 584: memcmp(&dpr, &test_dpr, sizeof(dpr))
dpr.raw != test_dpr.raw

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46555

to look at the new patch set (#6).

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 80 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/6

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 6:

(4 comments)

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
File src/soc/intel/xeon_sp/cpx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 571: DEV
> I'd use `dev` in lowercase (or `device`), and also indicate which stack this is on.

Done

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 571: die
> Can something else be done instead of dying?

Done

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 581: 			die("Unable to find VTD PCI DEV");
> Same comments here

Done

https://review.coreboot.org/c/coreboot/+/46555/5/src/soc/intel/xeon_sp/cpx/c... 
PS5, Line 584: memcmp(&dpr, &test_dpr, sizeof(dpr))
> dpr.raw != test_dpr. […]

Done

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 6:

(4 comments)

https://review.coreboot.org/c/coreboot/+/46555/6/src/soc/intel/xeon_sp/cpx/c... 
File src/soc/intel/xeon_sp/cpx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/6/src/soc/intel/xeon_sp/cpx/c... 
PS6, Line 569:         struct device *dev = VTD_DEV(0);
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/46555/6/src/soc/intel/xeon_sp/cpx/c... 
PS6, Line 569:         struct device *dev = VTD_DEV(0);
please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/46555/6/src/soc/intel/xeon_sp/skx/c... 
File src/soc/intel/xeon_sp/skx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/6/src/soc/intel/xeon_sp/skx/c... 
PS6, Line 585:         struct device *dev = VTD_DEV(0);
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/46555/6/src/soc/intel/xeon_sp/skx/c... 
PS6, Line 585:         struct device *dev = VTD_DEV(0);
please, no spaces at the start of a line

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46555

to look at the new patch set (#7).

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 80 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/7

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 7: Code-Review+2

It would be nice to avoid adding two copies of the same function.

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46555/7/src/soc/intel/xeon_sp/cpx/c... 
File src/soc/intel/xeon_sp/cpx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/7/src/soc/intel/xeon_sp/cpx/c... 
PS7, Line 565: union dpr_register txt_get_chipset_dpr(void)
Why not add this to memmap.c?

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 8:
> Patch Set 7: Code-Review+2
>
> It would be nice to avoid adding two copies of the same function.

CB:46478 addresses the duplicate code. It would be nice to land that for these changes.

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46555/9/src/soc/intel/xeon_sp/skx/c... 
File src/soc/intel/xeon_sp/skx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/9/src/soc/intel/xeon_sp/skx/c... 
PS9, Line 11: #include <soc/pci_devs.h>
needed? Probably missed in the rebase.

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46555

to look at the new patch set (#10).

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
3 files changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/10

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46555/9/src/soc/intel/xeon_sp/skx/c... 
File src/soc/intel/xeon_sp/skx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/9/src/soc/intel/xeon_sp/skx/c... 
PS9, Line 11: #include <soc/pci_devs.h>
> needed? Probably missed in the rebase.

Done

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 10: Code-Review+2

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46555/7/src/soc/intel/xeon_sp/cpx/c... 
File src/soc/intel/xeon_sp/cpx/chip.c:

https://review.coreboot.org/c/coreboot/+/46555/7/src/soc/intel/xeon_sp/cpx/c... 
PS7, Line 565: union dpr_register txt_get_chipset_dpr(void)
> Why not add this to memmap. […]

Done

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 10: Code-Review+2

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Hello Marc Jones, build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46555

to look at the new patch set (#12).

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
3 files changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/12

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Marc Jones, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46555

to look at the new patch set (#14).

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
3 files changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/14

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 14: Code-Review+2

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46555/14/src/soc/intel/xeon_sp/memm... 
File src/soc/intel/xeon_sp/memmap.c:

https://review.coreboot.org/c/coreboot/+/46555/14/src/soc/intel/xeon_sp/memm... 
PS14, Line 80: 			union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
line over 96 characters

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

Patch Set 14: Code-Review+2

Change in coreboot[master]: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46555 )

Change subject: soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
......................................................................

soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback

Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46555
Reviewed-by: Angel Pons 
Reviewed-by: Christian Walter 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
3 files changed, 49 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 33e257c..98c47fc 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -69,6 +69,7 @@
 #define VTD_CAP_LOW			0x08
 #define VTD_CAP_HIGH			0x0C
 #define VTD_EXT_CAP_HIGH		0x14
+#define VTD_LTDPR			0x290

/* CPU Devices */
 #define CBDMA_DEV_NUM           0x04
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index edc62cf..cd81754 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -5,7 +5,10 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/smm.h>
+#include <soc/soc_util.h>
 #include <soc/pci_devs.h>
+#include <soc/util.h>
+#include <security/intel/txt/txt_platform.h>

void smm_region(uintptr_t *start, size_t *size)
 {
@@ -41,3 +44,47 @@
    if (CONFIG(TSEG_STAGE_CACHE))
    	postcar_enable_tseg_cache(pcf);
 }
+
+#if !defined(__SIMPLE_DEVICE__)
+union dpr_register txt_get_chipset_dpr(void)
+{
+	const IIO_UDS *hob = get_iio_uds();
+	union dpr_register dpr;
+	struct device *dev = VTD_DEV(0);
+
+	dpr.raw = 0;
+
+	if (dev == NULL) {
+		printk(BIOS_ERR, "BUS 0: Unable to find VTD PCI dev");
+		return dpr;
+	}
+
+	dpr.raw = pci_read_config32(dev, VTD_LTDPR);
+
+	/* Compare the LTDPR register on all iio stacks */
+	for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
+		for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
+			const STACK_RES *ri =
+				&hob->PlatformData.IIO_resource[socket].StackRes[stack];
+			if (!is_iio_stack_res(ri))
+				continue;
+			uint8_t bus = ri->BusBase;
+			dev = VTD_DEV(bus);
+
+			if (dev == NULL) {
+				printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus);
+				dpr.raw = 0;
+				return  dpr;
+			}
+
+			union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
+			if (dpr.raw != test_dpr.raw) {
+				printk(BIOS_ERR, "LTDPR not the same on all IIO's");
+				dpr.raw = 0;
+				return dpr;
+			}
+		}
+	}
+	return dpr;
+}
+#endif
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 429278c..cd5d553 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -93,6 +93,7 @@
 #define VTD_CAP_LOW			0x08
 #define VTD_CAP_HIGH			0x0C
 #define VTD_EXT_CAP_HIGH		0x14
+#define VTD_LTDPR			0x290

#define PCU_CR1_C2C3TT_REG                                 0xdc
 #define PCU_CR1_PCIE_ILTR_OVRD                             0xfc