[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation

[Arthur Heymans (Code Review)]

Attention is currently required from: Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu.

Hello Christian Walter, David Hendricks, Johnny Lin, Nill Ge, Shuo Liu, TangYiwei, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/78327?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................

soc/intel/xeon_sp: Redesign resource allocation

The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.

Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- When a stack contains multiple host bridges as sometimes the case for
DINO stacks, add host bridges for each bus.

TEST: See that all resources are properly allocated on intel/archercity.

Signed-off-by: Arthur Heymans 
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
---
M src/device/pci_device.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
14 files changed, 172 insertions(+), 534 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/3