Change in coreboot[master]: mb/asus/p8z77-m_pro: Do not overwrite pei_data

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43030 )

Change subject: mb/asus/p8z77-m_pro: Do not overwrite pei_data
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mb/asus/p8z77-m_pro: Do not overwrite pei_data

Most of the values are already set in northbridge code.

Change-Id: I2490d63584205ff3f17ce29d7358214f3baaa09b
Signed-off-by: Angel Pons 
---
M src/mainboard/asus/p8z77-m_pro/early_init.c
1 file changed, 43 insertions(+), 73 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43030/1

diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c
index 87da010..e703e5b 100644
--- a/src/mainboard/asus/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8z77-m_pro/early_init.c
@@ -83,79 +83,49 @@
    get_option(&usb3_streams, "usb3_streams");
    usb3_streams &= 0x1; /* ensure it's 0/1 only */

-	struct pei_data pd = {
-		.pei_version = PEI_VERSION,
-		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
-		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
-		.epbar = DEFAULT_EPBAR,
-		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = CONFIG_HPET_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBABASE,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 1, /* 0=Mobile, 1=Desktop/Server */
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */
-		.gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
-		.dimm_channel0_disabled = 0, /* Both DIMM enabled */
-		.dimm_channel1_disabled = 0, /* Both DIMM enabled */
-		.max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
-		.usb_port_config = {
-			/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
-			{ 1, 0, 0x0080 }, /* USB3 front internal header */
-			{ 1, 0, 0x0080 }, /* USB3 front internal header */
-			{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
-			{ 1, 1, 0x0080 }, /* USB3 ETH botton connector */
-			{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
-			{ 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
-			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
-			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
-			{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
-			{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
-			{ 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
-			{ 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
-			{ 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
-			{ 0, 6, 0x0080 }  /* Unused. Asus DEBUG_PORT ??? */
-		},
-		.usb3 = {
-			/* 0=Disable; 1=Enable (start at USB3 speed)
-			 * 2=Auto (start as USB2 speed until OS loads)
-			 * 3=Smart Auto (like Auto but keep speed on reboot)
-			 */
-			usb3_mode,
-			/* 4 bit switch mask. 0=not switchable, 1=switchable
-			 * Means once it's loaded the OS, it can swap ports
-			 * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
-			 */
-			0xf,
-			usb3_drv, /* 1=Load xHCI pre-OS drv */
-			/* 0=Don't use xHCI streams for better compatibility
-			 * 1=use xHCI streams for better speed
-			 */
-			usb3_streams
-		},
-		/* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */
-		.ddr3lv_support = 1,
-		/* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
-		 * but might cause some system instability !
-		 */
-		.pcie_init = 1,
-		/* Command Rate. 0=Auto; 1=1N; 2=2N.
-		 * Leave it always at Auto for compatibility & stability
-		 */
-		.nmode = 0,
-		/* DDR refresh rate. 0=Auto based on DRAM's temperature;
-		 * 1=Normal rate for speed; 2=Double rate for stability
-		 */
-		.ddr_refresh_rate_config = 0
+	pei_data->system_type   = 1; /* 0 Mobile, 1 Desktop/Server */
+	pei_data->spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }; /* SMBus mul 2 */
+	pei_data->max_ddr3_freq = 1600;
+
+	/* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */
+	pei_data->ddr3lv_support = 1;
+
+	pei_data->usb_port_config = {
+		/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+		{ 1, 0, 0x0080 }, /* USB3 front internal header */
+		{ 1, 0, 0x0080 }, /* USB3 front internal header */
+		{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
+		{ 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+		{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
+		{ 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+		{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+		{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+		{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+		{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+		{ 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
+		{ 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
+		{ 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
+		{ 0, 6, 0x0080 }  /* Unused. Asus DEBUG_PORT ??? */
    };

-	/* copy the data to output PEI */
-	*pei_data = pd;
+	pei_data->usb3 = {
+		/*
+		 * 0=Disable; 1=Enable (start at USB3 speed)
+		 * 2=Auto (start as USB2 speed until OS loads)
+		 * 3=Smart Auto (like Auto but keep speed on reboot)
+		 */
+		usb3_mode,
+		/*
+		 * 4 bit switch mask. 0=not switchable, 1=switchable
+		 * Means once it's loaded the OS, it can swap ports
+		 * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+		 */
+		0xf,
+		usb3_drv, /* 1=Load xHCI pre-OS drv */
+		/*
+		 * 0=Don't use xHCI streams for better compatibility
+		 * 1=use xHCI streams for better speed
+		 */
+		usb3_streams
+	};
 }

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43030 )

Change subject: mb/asus/p8z77-m_pro: Do not overwrite pei_data
......................................................................

Abandoned