Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63924 )
Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K ......................................................................
Patch Set 3:
(3 comments)
File src/soc/mediatek/mt8186/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/63924/comment/40a868ae_a9e29482 PS2, Line 25: TTB(0x00100000, 28K) : DMA_COHERENT(0x00107000, 4K) : TPM_TCPA_LOG(0x00108000, 2K) : FMAP_CACHE(0x00108800, 2K) : WATCHDOG_TOMBSTONE(0x00109000, 4) : CBFS_MCACHE(0x00109004, 16K - 4) : /* EMPTY(0x0010d000, 4K) */ : STACK(0x0010E000, 7K) : TIMESTAMP(0x0010FC00, 1K) : /* MT8186 has 64KB SRAM. */ Done, with slight adjustment.
STACK 7k-4
From my experiments, the STACK size needs to be a multiple of 16. Neither `7K-4` nor `7K-8` work: the last log was `Jump to BL`, which means that the device got stuck somewhere in bootblock before `console_init()`. The device can boot with `7K-16` though.
ARM64's memlayout.h only requires the address to be 16-byte aligned. I'm not sure if we should also add an extra assertion for the size.
https://review.coreboot.org/c/coreboot/+/63924/comment/da136ef5_33562588 PS2, Line 44: /* 4K reserved for BOOTROM until BOOTBLOCK is started */
Correction. […]
Done
https://review.coreboot.org/c/coreboot/+/63924/comment/7e5dbe11_6a2d2084 PS2, Line 50: 184K
aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz […]
Yes, I've mentioned that in the commit message.