Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: format generic PNP documentation ......................................................................
Documentation/superio: format generic PNP documentation
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M Documentation/superio/common/pnp.md 1 file changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/38519/1
diff --git a/Documentation/superio/common/pnp.md b/Documentation/superio/common/pnp.md index 314cac2..948078f 100644 --- a/Documentation/superio/common/pnp.md +++ b/Documentation/superio/common/pnp.md @@ -15,13 +15,13 @@
Super I/O chips connected via LPC to the southbridge usually have their I/O-mapped configuration interface with a size of two bytes at the base -address 0x2e or 0x4e. Other PNP devices have their configuration +address `0x2e` or `0x4e`. Other PNP devices have their configuration interface at other addresses.
The two byte registers allow access to an indirect 256 bytes big -register space that contains the configuration. By writing the index -to the lower byte (e.g. 0x2e), you can access the register contents at -that index by reading/writing the higher byte (e.g. 0x2f). +register space that contains the configuration. By writing the index to +the lower byte (e.g. `0x2e`), you can access the register contents at +that index by reading/writing the higher byte (e.g. `0x2f`).
To prevent accidental changes of the Super I/O (SIO) configuration, the SIOs need a configuration mode unlock sequence. After changing the @@ -31,18 +31,18 @@ ## Logical device numbers (LDN)
Each PNP device can contain multiple logical devices. The bytes from -0x00 to 0x2f in the indirect configuration register space are common -for all LDNs, but some SIO chips require a certain LDN to be selected -in order to write certain registers in there. An LDN gets selected by -writing the LDN number to the LDN select register 0x07. Registers 0x30 -to 0xFF are specific to each LDN number. +`0x00` to `0x2f` in the indirect configuration register space are common +for all LDNs, but some SIO chips require a certain LDN to be selected in +order to write certain registers in there. An LDN gets selected by +writing the LDN number to the LDN select register `0x07`. Registers +`0x30` to `0xFF` are specific to each LDN number.
coreboot encodes the physical LDN number in the lower byte of the LDN number.
### Virtual logical device numbers
-Register 0x30 is the LDN enable register and since it is an 8 bit +Register `0x30` is the LDN enable register and since it is an 8 bit register, it can contain up to 8 enable bits for different parts of the functionality of that logical device. To set a certain enable bit in one physical LDN, the concept of virtual LDNs was introduced. @@ -54,7 +54,7 @@
## I/O resources
-Starting at register address 0x60, each LDN has 2 byte wide I/O base +Starting at register address `0x60`, each LDN has 2 byte wide I/O base address registers. The size of an I/O resource is always a power of two.
@@ -67,29 +67,29 @@ the resource has N address bits and a size of 2**N bytes. The mask address is also the highest possible address to map the I/O region.
-A typical example for an I/O resource mask is 0x07f8 which is -0b0000011111111000 in binary notation. The three LSBs are zeros here, +A typical example for an I/O resource mask is `0x07f8` which is +`0b0000011111111000` in binary notation. The three LSBs are zeros here, so it's an eight byte I/O resource with three address offset bits inside the resource. The highest base address it can be mapped to is -0x07f8, so the region will end at 0x07ff. +`0x07f8`, so the region will end at `0x07ff`.
The Super I/O datasheets typically contain the information about the I/O resource masks. On most Super I/O chips the mask can also be found -out by writing 0xffff to the corresponding I/O base address register +out by writing `0xffff` to the corresponding I/O base address register and reading back the value; since the lowest and highest bits are hard-wired to zero according to the I/O resource size and maximal possible I/O address, this gives the mask.
## IRQ resources
-Each physical LDN has up to two configurable interrupt request -register pairs 0x70, 0x71 and 0x72, 0x73. Each pair can be configured -to use a certain IRQ number. Writing 1 to 15 into the first register +Each physical LDN has up to two configurable interrupt request register +pairs `0x70`, `0x71` and `0x72`, `0x73`. Each pair can be configured to +use a certain IRQ number. Writing 1 to 15 into the first register selects the IRQ number generated by the corresponding IRQ source and -enables IRQ generation; writing 0 to it disables the generation of -IRQs for the source. The second register selects the IRQ type (level -or edge) and IRQ level (high or low). For LPC SIOs the IRQ type is -hard-wired to edge. +enables IRQ generation; writing 0 to it disables the generation of IRQs +for the source. The second register selects the IRQ type (level or edge) +and IRQ level (high or low). For LPC SIOs the IRQ type is hard-wired to +edge.
On the LPC bus a shared SERIRQ line is used to signal IRQs to the host; the IRQ number gets encoded by the number of LPC clock cycles @@ -106,7 +106,7 @@ ## DRQ resources
Each physical LDN has two legacy ISA-style DMA request channel -registers at 0x74 and 0x75. Those are only used for legacy devices +registers at `0x74` and `0x75`. Those are only used for legacy devices like parallel printer ports or floppy disk controllers.
Each device using LPC legacy DMA needs its own LDMA line to the host.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: format generic PNP documentation ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG@7 PS1, Line 7: Documentation/superio: format generic PNP documentation
Documention/superio: Mark up generic PNP documentation
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: format generic PNP documentation ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG@7 PS1, Line 7: Documentation/superio: format generic PNP documentation
Documention/superio: Mark up generic PNP documentation
doesn't "mark up" mean to increase a price?!
would "Documentation/superio: add formatting to generic PNP documentation" be better?
Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38519
to look at the new patch set (#2).
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Documentation/superio: add formatting to generic PNP documentation
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M Documentation/superio/common/pnp.md 1 file changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/38519/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG@7 PS1, Line 7: Documentation/superio: format generic PNP documentation
doesn't "mark up" mean to increase a price?! […]
i changed it to what i suggested
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/2/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38519/2/Documentation/superio/commo... PS2, Line 38: 0xFF lower case like all the others?
Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38519
to look at the new patch set (#4).
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Documentation/superio: add formatting to generic PNP documentation
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M Documentation/superio/common/pnp.md 1 file changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/38519/4
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/2/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38519/2/Documentation/superio/commo... PS2, Line 38: 0xFF
lower case like all the others?
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 4: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38519/1//COMMIT_MSG@7 PS1, Line 7: Documentation/superio: format generic PNP documentation According to https://www.merriam-webster.com/dictionary/mark%20up that is the only meaning, but https://en.m.wiktionary.org/wiki/mark_up also lists the meaning I had in mind.
To add coding to text so that it will display properly on a computer.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38519/2/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38519/2/Documentation/superio/commo... PS2, Line 38: 0xFF
lower case like all the others?
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Documentation/superio: add formatting to generic PNP documentation
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519 Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M Documentation/superio/common/pnp.md 1 file changed, 23 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/Documentation/superio/common/pnp.md b/Documentation/superio/common/pnp.md index 314cac2..3c17259 100644 --- a/Documentation/superio/common/pnp.md +++ b/Documentation/superio/common/pnp.md @@ -15,13 +15,13 @@
Super I/O chips connected via LPC to the southbridge usually have their I/O-mapped configuration interface with a size of two bytes at the base -address 0x2e or 0x4e. Other PNP devices have their configuration +address `0x2e` or `0x4e`. Other PNP devices have their configuration interface at other addresses.
The two byte registers allow access to an indirect 256 bytes big -register space that contains the configuration. By writing the index -to the lower byte (e.g. 0x2e), you can access the register contents at -that index by reading/writing the higher byte (e.g. 0x2f). +register space that contains the configuration. By writing the index to +the lower byte (e.g. `0x2e`), you can access the register contents at +that index by reading/writing the higher byte (e.g. `0x2f`).
To prevent accidental changes of the Super I/O (SIO) configuration, the SIOs need a configuration mode unlock sequence. After changing the @@ -31,18 +31,18 @@ ## Logical device numbers (LDN)
Each PNP device can contain multiple logical devices. The bytes from -0x00 to 0x2f in the indirect configuration register space are common -for all LDNs, but some SIO chips require a certain LDN to be selected -in order to write certain registers in there. An LDN gets selected by -writing the LDN number to the LDN select register 0x07. Registers 0x30 -to 0xFF are specific to each LDN number. +`0x00` to `0x2f` in the indirect configuration register space are common +for all LDNs, but some SIO chips require a certain LDN to be selected in +order to write certain registers in there. An LDN gets selected by +writing the LDN number to the LDN select register `0x07`. Registers +`0x30` to `0xff` are specific to each LDN number.
coreboot encodes the physical LDN number in the lower byte of the LDN number.
### Virtual logical device numbers
-Register 0x30 is the LDN enable register and since it is an 8 bit +Register `0x30` is the LDN enable register and since it is an 8 bit register, it can contain up to 8 enable bits for different parts of the functionality of that logical device. To set a certain enable bit in one physical LDN, the concept of virtual LDNs was introduced. @@ -54,7 +54,7 @@
## I/O resources
-Starting at register address 0x60, each LDN has 2 byte wide I/O base +Starting at register address `0x60`, each LDN has 2 byte wide I/O base address registers. The size of an I/O resource is always a power of two.
@@ -67,29 +67,29 @@ the resource has N address bits and a size of 2**N bytes. The mask address is also the highest possible address to map the I/O region.
-A typical example for an I/O resource mask is 0x07f8 which is -0b0000011111111000 in binary notation. The three LSBs are zeros here, +A typical example for an I/O resource mask is `0x07f8` which is +`0b0000011111111000` in binary notation. The three LSBs are zeros here, so it's an eight byte I/O resource with three address offset bits inside the resource. The highest base address it can be mapped to is -0x07f8, so the region will end at 0x07ff. +`0x07f8`, so the region will end at `0x07ff`.
The Super I/O datasheets typically contain the information about the I/O resource masks. On most Super I/O chips the mask can also be found -out by writing 0xffff to the corresponding I/O base address register +out by writing `0xffff` to the corresponding I/O base address register and reading back the value; since the lowest and highest bits are hard-wired to zero according to the I/O resource size and maximal possible I/O address, this gives the mask.
## IRQ resources
-Each physical LDN has up to two configurable interrupt request -register pairs 0x70, 0x71 and 0x72, 0x73. Each pair can be configured -to use a certain IRQ number. Writing 1 to 15 into the first register +Each physical LDN has up to two configurable interrupt request register +pairs `0x70`, `0x71` and `0x72`, `0x73`. Each pair can be configured to +use a certain IRQ number. Writing 1 to 15 into the first register selects the IRQ number generated by the corresponding IRQ source and -enables IRQ generation; writing 0 to it disables the generation of -IRQs for the source. The second register selects the IRQ type (level -or edge) and IRQ level (high or low). For LPC SIOs the IRQ type is -hard-wired to edge. +enables IRQ generation; writing 0 to it disables the generation of IRQs +for the source. The second register selects the IRQ type (level or edge) +and IRQ level (high or low). For LPC SIOs the IRQ type is hard-wired to +edge.
On the LPC bus a shared SERIRQ line is used to signal IRQs to the host; the IRQ number gets encoded by the number of LPC clock cycles @@ -106,7 +106,7 @@ ## DRQ resources
Each physical LDN has two legacy ISA-style DMA request channel -registers at 0x74 and 0x75. Those are only used for legacy devices +registers at `0x74` and `0x75`. Those are only used for legacy devices like parallel printer ports or floppy disk controllers.
Each device using LPC legacy DMA needs its own LDMA line to the host.
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38519 )
Change subject: Documentation/superio: add formatting to generic PNP documentation ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/667 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/666 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/665
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Felix Held (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)