Change in coreboot[master]: [DNM] soc/intel: Fix SPI write protect and EISS support

[Angel Pons (Code Review)]

Attention is currently required from: Benjamin Doron, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50724 )

Change subject: [DNM] soc/intel: Fix SPI write protect and EISS support
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/50724/comment/a7ff0bb1_e35bc281 
PS3, Line 9: Systems are hanging when chipset enforces SPI write protect.
> But that's not the issue here? coreboot can complete booting after enabling WP and setting the EISS  […]

I think the hardware locks up even before SMM has a chance to run. I didn't manage to get any logging from coreboot after setting that bit and CONFIG_DEBUG_SMI=y.