[XS] Change in coreboot[master]: soc/intel/spr-sp: Remove HWP related settings

[Ziang Wang (Code Review)]

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75741?usp=email )

Change subject: soc/intel/spr-sp: Remove HWP related settings
......................................................................

soc/intel/spr-sp: Remove HWP related settings

HWP feature can be set via 'CpuPmProcessorHWPMEnable' UPD option in
FSP-S, so related manipulations in coreboot are being removed.

Change-Id: Ic4ff63cbff0dffb4cd65fdfa814eda85964130ee
Signed-off-by: wanghao11 
Signed-off-by: Ziang Wang 
---
M src/soc/intel/xeon_sp/spr/cpu.c
1 file changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/75741/1

diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c
index 2ed8e22..556ecef 100644
--- a/src/soc/intel/xeon_sp/spr/cpu.c
+++ b/src/soc/intel/xeon_sp/spr/cpu.c
@@ -122,14 +122,15 @@
    wrmsr(PACKAGE_RAPL_LIMIT, msr);

/*
-	 * Set HWP base feature, EPP reg enumeration, lock thermal and msr
+	 * HWP feature can be set via CpuPmProcessorHWPMEnable UPD option during FSP-S stage,
+	 * so programming of MSR_MISC_PWR_MGMT and LOCK_THERM_INT is skipped here.
+	 * If msr MSR_MISC_PWR_MGMT hasn't been locked, lock it here.
     * This is package level MSR. Need to check if it updates correctly on
     * multi-socket platform.
     */
    msr = rdmsr(MSR_MISC_PWR_MGMT);
    if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */
-		msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR
-			  | LOCK_THERM_INT);
+		msr.lo |= LOCK_MISC_PWR_MGMT_MSR;
    	wrmsr(MSR_MISC_PWR_MGMT, msr);
    }