Change in coreboot[master]: mb/google/brya: Implement SLP_S0_GATE signal

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50881 )

Change subject: mb/google/brya: Implement SLP_S0_GATE signal
......................................................................

mb/google/brya: Implement SLP_S0_GATE signal

The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to
provide an indication to the rest of the platform when the system is
entering its software-initiated low-power state (i.e. S0ix). This lets
the platform distinguish between opportunistic S0ix entry and the runtime
suspend mechanism.

BUG=b:180401723
TEST=abuild

Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca
Signed-off-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/dsdt.asl
A src/mainboard/google/brya/mainboard.asl
M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h
3 files changed, 30 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/50881/1

diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index 5d386f1..4dd2eb6 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -22,6 +22,8 @@
    #include <cpu/intel/common/acpi/cpu.asl>

Scope (_SB) {
+		#include "mainboard.asl"
+
    	Device (PCI0)
    	{
    		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl
new file mode 100644
index 0000000..68ce392
--- /dev/null
+++ b/src/mainboard/google/brya/mainboard.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from _SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+        If (Arg0 == 1) {
+                /*
+		 * On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of
+		 * the platform can transition to its low power state as well.
+		 */
+		_SB.PCI0.CTXS(GPIO_SLP_S0_GATE);
+        } Else {
+                /*
+		 * On S0ix exit, set the SLP_S0_GATE pin, so that the rest of
+		 * the platform will resume from its low power state.
+		 */
+                _SB.PCI0.STXS(GPIO_SLP_S0_GATE);
+        }
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h
index 2024e48..811a8f5 100644
--- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h
@@ -7,8 +7,10 @@
 #include <soc/gpio.h>

/* eSPI virtual wire reporting */
-#define EC_SCI_GPI	GPE0_ESPI
+#define EC_SCI_GPI		GPE0_ESPI
 /* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
-#define GPE_EC_WAKE	GPE0_DW2_17
+#define GPE_EC_WAKE		GPE0_DW2_17
+
+#define GPIO_SLP_S0_GATE	GPP_F9

#endif /* __BASEBOARD_GPIO_H__ */