yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: WIP: coreboot: Add dsi file ......................................................................
WIP: coreboot: Add dsi file
Add dsi APIs for coreboot display
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 129 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 04d57dc..b2a8a9e 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,8 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c
+ramstage-y += ../common/dsi.c dsi.c + MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192
cbfs-files-y += dpm.dm diff --git a/src/soc/mediatek/mt8192/dsi.c b/src/soc/mediatek/mt8192/dsi.c new file mode 100644 index 0000000..9f54f49 --- /dev/null +++ b/src/soc/mediatek/mt8192/dsi.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <delay.h> +#include <soc/dsi.h> +#include <soc/pll.h> + +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) +{ + unsigned int txdiv0, txdiv1; + u64 pcw; + + if (data_rate >= 2000 * MHz) { + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000 * MHz) { + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500 * MHz) { + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250 * MHz) { + /* (data_rate == 250MHz) is a special case that should go to the + else-block below (txdiv0 = 4) */ + txdiv0 = 3; + txdiv1 = 0; + } else { + /* MIN = 125 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz); + txdiv0 = 4; + txdiv1 = 0; + } + + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); + pcw <<= 24; + pcw /= CLK26M_HZ; + + write32(&mipi_tx->pll_con0, pcw); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + udelay(30); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + write32(&mipi_tx->lane_con, 0x3fff0180); + udelay(40); + write32(&mipi_tx->lane_con, 0x3fff00c0); + + /* Switch OFF each Lane */ + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); +} + +void mtk_dsi_reset(void) +{ + write32(&dsi0->dsi_force_commit, + DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS); + write32(&dsi0->dsi_con_ctrl, 1); + write32(&dsi0->dsi_con_ctrl, 0); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 3fd2bca..eac4a9a 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -64,6 +64,8 @@ MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + MIPITX_BASE = IO_PHYS + 0x01E50000, + DSI0_BASE = IO_PHYS + 0x04010000, };
#endif diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h new file mode 100644 index 0000000..4535d90 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8183_DSI_H +#define SOC_MEDIATEK_MT8183_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif
Jg Daolongzhu has uploaded a new patch set (#4) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: WIP: coreboot: Add dsi file ......................................................................
WIP: coreboot: Add dsi file
Add dsi APIs for coreboot display
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 129 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/4
Yu-Ping Wu has uploaded a new patch set (#6) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
soc/mediatek/mt8192: Add dsi driver
Add dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/6
Yidi Lin has uploaded a new patch set (#7) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
soc/mediatek/mt8192: Add dsi driver
Add dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/7
Yidi Lin has uploaded a new patch set (#8) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
soc/mediatek/mt8192: Add dsi driver
Add dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/8
Yidi Lin has uploaded a new patch set (#10) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
soc/mediatek/mt8192: Add dsi driver
Add dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/10
Yidi Lin has uploaded a new patch set (#11) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
soc/mediatek/mt8192: Add dsi driver
Add dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/11
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
Patch Set 11:
The dsi.c looks like exactly the same as 8183.
Is there a name for platforms sharing same DSI driver?
I wonder if we can move this to common/ and call it, for example, dsi_v2.c (I know 8173 is using a different driver)
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Add dsi driver ......................................................................
Patch Set 11:
Patch Set 11:
The dsi.c looks like exactly the same as 8183.
Is there a name for platforms sharing same DSI driver?
I wonder if we can move this to common/ and call it, for example, dsi_v2.c (I know 8173 is using a different driver)
Yes, we can move it to common/ and call it as dsi_v2.c. It can be shared among mt8183 and mt819x series.
Yidi Lin has uploaded a new patch set (#12) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
soc/mediatek/mt8192: Enable dsi driver
Enable dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/12
Yidi Lin has uploaded a new patch set (#13) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
soc/mediatek/mt8192: Enable dsi driver
Enable dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/13
Yidi Lin has uploaded a new patch set (#15) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
soc/mediatek/mt8192: Enable dsi driver
Enable dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/15
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
Patch Set 15: Code-Review+2
Yidi Lin has uploaded a new patch set (#16) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
soc/mediatek/mt8192: Enable dsi driver
Enable dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/16
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
Patch Set 16: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46574 )
Change subject: soc/mediatek/mt8192: Enable dsi driver ......................................................................
soc/mediatek/mt8192: Enable dsi driver
Enable dsi driver for display.
BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46574 Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 3 files changed, 58 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 8394c12..157ada4 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -39,6 +39,7 @@
ramstage-y += ../common/auxadc.c ramstage-y += dpm.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/i2c.c i2c.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 0d756b8..6cee8f3 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -53,12 +53,14 @@ IOCFG_BR_BASE = IO_PHYS + 0x01D40000, IOCFG_LM_BASE = IO_PHYS + 0x01E20000, SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, + MIPITX_BASE = IO_PHYS + 0x01E50000, IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_BASE = IO_PHYS + 0x01F60000, + DSI0_BASE = IO_PHYS + 0x04010000, };
#endif diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h new file mode 100644 index 0000000..ed3d0d8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_DSI_H +#define SOC_MEDIATEK_MT8192_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif
-
Hung-Te Lin (Code Review) -
Jg Daolongzhu (Code Review)
-
Yidi Lin (Code Review)
-
yongqiang niu (Code Review)
-
Yu-Ping Wu (Code Review)