Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46966 )
Change subject: soc/intel/broadwell: Drop enable check from LPD0/LPD3 ......................................................................
soc/intel/broadwell: Drop enable check from LPD0/LPD3
When SerialIO devices are disabled, their _STA method evaluates to 0, which means the device is not present. It is expected that OSPM would not attempt to change the power state of a device that is not present. Lynxpoint does not have these checks, thus remove them from Broadwell. Also remove the now-unused Arg1 parameter to avoid warnings from IASL.
Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 14 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46966/1
diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 91fa758..b03bcdd 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -7,14 +7,8 @@
// Put SerialIO device in D0 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD0, 2, Serialized) +Method (LPD0, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -30,14 +24,8 @@
// Put SerialIO device in D3 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD3, 2, Serialized) +Method (LPD3, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -240,12 +228,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1, \S1EN) + ^^LPD0 (\S1B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1, \S1EN) + ^^LPD3 (\S1B1) } }
@@ -311,12 +299,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1, \S2EN) + ^^LPD0 (\S2B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1, \S2EN) + ^^LPD3 (\S2B1) } }
@@ -367,12 +355,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1, \S3EN) + ^^LPD0 (\S3B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1, \S3EN) + ^^LPD3 (\S3B1) } }
@@ -435,12 +423,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1, \S4EN) + ^^LPD0 (\S4B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1, \S4EN) + ^^LPD3 (\S4B1) } }
@@ -503,12 +491,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1, \S5EN) + ^^LPD0 (\S5B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1, \S5EN) + ^^LPD3 (\S5B1) } }
@@ -559,12 +547,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1, \S6EN) + ^^LPD0 (\S6B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1, \S6EN) + ^^LPD3 (\S6B1) } }
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46966
to look at the new patch set (#6).
Change subject: soc/intel/broadwell: Drop enable check from LPD0/LPD3 ......................................................................
soc/intel/broadwell: Drop enable check from LPD0/LPD3
When SerialIO devices are disabled, their _STA method evaluates to 0, which means the device is not present. It is expected that OSPM would not attempt to change the power state of a device that is not present. Lynxpoint does not have these checks, thus remove them from Broadwell. Also remove the now-unused Arg1 parameter to avoid warnings from IASL.
Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 14 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46966/6
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46966 )
Change subject: soc/intel/broadwell: Drop enable check from LPD0/LPD3 ......................................................................
Patch Set 8: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46966 )
Change subject: soc/intel/broadwell: Drop enable check from LPD0/LPD3 ......................................................................
soc/intel/broadwell: Drop enable check from LPD0/LPD3
When SerialIO devices are disabled, their _STA method evaluates to 0, which means the device is not present. It is expected that OSPM would not attempt to change the power state of a device that is not present. Lynxpoint does not have these checks, thus remove them from Broadwell. Also remove the now-unused Arg1 parameter to avoid warnings from IASL.
Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46966 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 14 insertions(+), 26 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 91fa758..b03bcdd 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -7,14 +7,8 @@
// Put SerialIO device in D0 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD0, 2, Serialized) +Method (LPD0, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -30,14 +24,8 @@
// Put SerialIO device in D3 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD3, 2, Serialized) +Method (LPD3, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -240,12 +228,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1, \S1EN) + ^^LPD0 (\S1B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1, \S1EN) + ^^LPD3 (\S1B1) } }
@@ -311,12 +299,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1, \S2EN) + ^^LPD0 (\S2B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1, \S2EN) + ^^LPD3 (\S2B1) } }
@@ -367,12 +355,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1, \S3EN) + ^^LPD0 (\S3B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1, \S3EN) + ^^LPD3 (\S3B1) } }
@@ -435,12 +423,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1, \S4EN) + ^^LPD0 (\S4B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1, \S4EN) + ^^LPD3 (\S4B1) } }
@@ -503,12 +491,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1, \S5EN) + ^^LPD0 (\S5B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1, \S5EN) + ^^LPD3 (\S5B1) } }
@@ -559,12 +547,12 @@
Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1, \S6EN) + ^^LPD0 (\S6B1) }
Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1, \S6EN) + ^^LPD3 (\S6B1) } }
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)