[XS] Change in coreboot[main]: soc/amd/glinda: Fix pci int defs

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86421?usp=email )

Change subject: soc/amd/glinda: Fix pci int defs
......................................................................

soc/amd/glinda: Fix pci int defs

commit 540d605f4849 ("soc/amd/glinda: Update pci int defs") forgot to
update the offset after adding GEventSmi and GEventSci.

source:
PPR #57254 Rev 1.59 Table 137

Change-Id: I702f16e681d57c5e44f91c805a9aeb71eb160bd3
Signed-off-by: Maximilian Brune 
---
M src/soc/amd/glinda/acpi/pci_int_defs.asl
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/86421/1

diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl
index 61ecd44..53ced22 100644
--- a/src/soc/amd/glinda/acpi/pci_int_defs.asl
+++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-/* TODO: Update for Glinda */
-
 /* PCI IRQ mapping registers, C00h-C01h. */
 OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
    Field(PRQM, ByteAcc, NoLock, Preserve) {
@@ -51,7 +49,7 @@
    IORG, 0x00000008,	/* Index 0x86: INTG */
    IORH, 0x00000008,	/* Index 0x87: INTH */

-	Offset (0xE2),
+	Offset (0xE0),
    IGSC, 0x00000008,	/* Index 0xE0: GEventSci */
    IGSM, 0x00000008,	/* Index 0xE1: GEventSmi */
    IGPI, 0x00000008,	/* Index 0xE2: GPIO */