Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61407 )
Change subject: soc/intel/common/cse: skip heci_init() if HECI1 is disabled ......................................................................
soc/intel/common/cse: skip heci_init() if HECI1 is disabled
If the HECI1 PCI device is disabled, either via devicetree or other method (HAP, me_cleaner), then we don't want/need to program a BAR, set the PCI config, or call heci_reset(), as the latter will result in a 15s timeout delay when booting.
Test: build/boot Purism Librem 13v2, verify heci_reset() timeout delay is no longer present.
Change-Id: I0babe417173d10e37327538dc9e7aae980225367 Signed-off-by: Matt DeVillier matt.devillier@puri.sm Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Subrata Banik subratabanik@google.com --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7d6faba..32f6d4f 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -94,6 +94,10 @@
u16 pcireg;
+ /* Check if device enabled */ + if (!is_cse_enabled()) + return; + /* Assume it is already initialized, nothing else to do */ if (get_cse_bar(dev)) return;