[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 )

Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
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Patch Set 3: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69680/comment/1468ac50_ed63f53b 
PS2, Line 10: 
            : The learning being made from Alder Lake platform showed that the CSE
            : EOP cmd response time is highly nondeterministic and letting the EOP
            : cmd issued by FSP makes the response time even worse.
            : 
            : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute
            : (late sending of EOP) to ensure there is ample time for CSE to come
            : to a state where the response to the EOP is almost immediate.
> Thanks for commit update. Since architectural change from ADL to MTL, I'm not sure if this is applicable to MTL.

Can you please elaborate how the EOP cmd receiving arch is different between ADL and MTL?

We would like to get rid of FSP sending EOP and taking control of things inside coreboot and for that matter, we need to make some changes (this CL is one of those changes).

we don't want FSP to send the EOP hence, it's important that we make sure FSP is not touching the D0i3 bit even for HECI devices. I don't see any concern about letting this CL in.