Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings.
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, we observed that without setting these params display part was not binding. With the latest code verifed that we dont need to explicity set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e105061..8d8b14d 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -96,9 +96,6 @@ uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; - uint8_t PchHdaIDispLinkTmode; - uint8_t PchHdaIDispLinkFrequency; - uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 9933200..a357b97 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -159,9 +159,6 @@ sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
/* Vt-D config */ m_cfg->VtdDisable = 0;
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40263
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings.
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, we observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40263
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings.
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/3
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40263
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings.
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40263
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings.
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 0 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/5
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40263
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings.
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 5 files changed, 0 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/6
Sathyanarayana Nujella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
Patch Set 6: Code-Review+1
LGTM
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/40263/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40263/6//COMMIT_MSG@7 PS6, Line 7: soc/intel/tigerlake: Update iDisp Link UPD settings. Please remove the dot/period at the end of the commit message summary.
Jairaj Arava has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings. ......................................................................
Patch Set 6: Code-Review+1
Hello Sathyanarayana Nujella, build bot (Jenkins), Paul Menzel, Jairaj Arava, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40263
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 5 files changed, 0 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40263/7
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings ......................................................................
Patch Set 7: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings ......................................................................
Patch Set 7: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40263/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40263/6//COMMIT_MSG@7 PS6, Line 7: soc/intel/tigerlake: Update iDisp Link UPD settings.
Please remove the dot/period at the end of the commit message summary.
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40263 )
Change subject: soc/intel/tigerlake: Update iDisp Link UPD settings ......................................................................
soc/intel/tigerlake: Update iDisp Link UPD settings
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings.
BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Sathyanarayana Nujella sathyanarayana.nujella@intel.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Jairaj Arava jairaj.arava@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 5 files changed, 0 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Sathyanarayana Nujella: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Jairaj Arava: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8a6bcf3..28931e4 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -121,13 +121,6 @@ register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" register "PchHdaAudioLinkSspEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" -
# TCSS USB3 register "TcssXhciEn" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 8b4f8f8..82f358e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -121,12 +121,6 @@ register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSspEnable[2]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 9b5774b..fec2fef 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -117,12 +117,6 @@ register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSspEnable[2]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 26eab4c..a3319d4 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -96,9 +96,6 @@ uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; - uint8_t PchHdaIDispLinkTmode; - uint8_t PchHdaIDispLinkFrequency; - uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 6056b4b..b4521e2 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -165,9 +165,6 @@ sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
/* Vt-D config */ m_cfg->VtdDisable = 0;