[XS] Change in coreboot[main]: soc/intel/xeon_sp: Compress FSP-S

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81634?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp: Compress FSP-S
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soc/intel/xeon_sp: Compress FSP-S

Compress FSP-S to save some space in CBFS.
Reduces the size of debug FSP-S by about 25%.

Test: Still boots on ibm/sbp1.
TEST= Build and boot on intel/archercity CRB.

Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634
Reviewed-by: Shuo Liu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Angel Pons: Looks good to me, approved
  build bot (Jenkins): Verified
  Shuo Liu: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 51f407e..45c7d9d 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -15,6 +15,7 @@
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
    select FSP_CAR
    select FSP_M_XIP
+	select FSP_COMPRESS_FSP_S_LZ4
    select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
    select FSP_T_XIP
    select HAVE_SMI_HANDLER