Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29260
Change subject: soc/intel/cannonlake: Remove depreciated UPD selection ......................................................................
soc/intel/cannonlake: Remove depreciated UPD selection
Sevel FSP silicon init UPD have been moved to memory init stage, modify the coreboot accordingly. Those UPD is the following: SkipMpInit VtdBaseAddress VtdDisable X2ApicOptOut
BUG=N/A TEST=Build pass with FSP revision 7.0.47.50.
Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29260/1
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 6167346..3314f6d 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -67,7 +67,6 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; - FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info;
@@ -203,16 +202,12 @@
params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; - params->SkipMpInit = !chip_get_fsp_mp_init();
/* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); - - /* Vt-D config */ - tconfig->VtdDisable = config->VtdDisable; }
/* Mainboard GPIO Configuration */