Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36980 )
Change subject: nb/sb/cpu: Drop Intel Rangeley support ......................................................................
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/Makefile.inc D src/cpu/intel/fsp_model_406dx/Kconfig D src/cpu/intel/fsp_model_406dx/Makefile.inc D src/cpu/intel/fsp_model_406dx/acpi.c D src/cpu/intel/fsp_model_406dx/bootblock.c D src/cpu/intel/fsp_model_406dx/chip.h D src/cpu/intel/fsp_model_406dx/model_406dx.h D src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/include/device/pci_ids.h D src/northbridge/intel/fsp_rangeley/Kconfig D src/northbridge/intel/fsp_rangeley/Makefile.inc D src/northbridge/intel/fsp_rangeley/acpi.c D src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl D src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl D src/northbridge/intel/fsp_rangeley/chip.h D src/northbridge/intel/fsp_rangeley/fsp/Kconfig D src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc D src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c D src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h D src/northbridge/intel/fsp_rangeley/memmap.c D src/northbridge/intel/fsp_rangeley/northbridge.c D src/northbridge/intel/fsp_rangeley/northbridge.h D src/northbridge/intel/fsp_rangeley/port_access.c M src/southbridge/intel/common/watchdog.c D src/southbridge/intel/fsp_rangeley/Kconfig D src/southbridge/intel/fsp_rangeley/Makefile.inc D src/southbridge/intel/fsp_rangeley/acpi.c D src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl D src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h D src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl D src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl D src/southbridge/intel/fsp_rangeley/acpi/lpc.asl D src/southbridge/intel/fsp_rangeley/acpi/pcie.asl D src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl D src/southbridge/intel/fsp_rangeley/acpi/sata.asl D src/southbridge/intel/fsp_rangeley/acpi/soc.asl D src/southbridge/intel/fsp_rangeley/acpi/usb.asl D src/southbridge/intel/fsp_rangeley/chip.h D src/southbridge/intel/fsp_rangeley/early_init.c D src/southbridge/intel/fsp_rangeley/early_smbus.c D src/southbridge/intel/fsp_rangeley/early_usb.c D src/southbridge/intel/fsp_rangeley/gpio.c D src/southbridge/intel/fsp_rangeley/gpio.h D src/southbridge/intel/fsp_rangeley/irq.h D src/southbridge/intel/fsp_rangeley/lpc.c D src/southbridge/intel/fsp_rangeley/nvs.h D src/southbridge/intel/fsp_rangeley/pci_devs.h D src/southbridge/intel/fsp_rangeley/romstage.c D src/southbridge/intel/fsp_rangeley/romstage.h D src/southbridge/intel/fsp_rangeley/sata.c D src/southbridge/intel/fsp_rangeley/smbus.c D src/southbridge/intel/fsp_rangeley/soc.c D src/southbridge/intel/fsp_rangeley/soc.h D src/southbridge/intel/fsp_rangeley/spi.c M src/vendorcode/intel/Kconfig D src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h D src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c D src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 68 files changed, 2 insertions(+), 9,280 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36980/1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36980 )
Change subject: nb/sb/cpu: Drop Intel Rangeley support ......................................................................
Patch Set 1: Code-Review+1
MAINTAINERS:281:F: src/cpu/intel/fsp_model_406dx/ MAINTAINERS:282:F: src/northbridge/intel/fsp_rangeley/ MAINTAINERS:283:F: src/southbridge/intel/fsp_rangeley/ src/cpu/intel/Kconfig:12:source src/cpu/intel/fsp_model_406dx/Kconfig
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36980 )
Change subject: nb/sb/cpu: Drop Intel Rangeley support ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36980 )
Change subject: nb/sb/cpu: Drop Intel Rangeley support ......................................................................
Patch Set 1: Code-Review+2
Given the activity of CB:34686...
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36980 )
Change subject: nb/sb/cpu: Drop Intel Rangeley support ......................................................................
Patch Set 1: Code-Review+1
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36980 )
Change subject: nb/sb/cpu: Drop Intel Rangeley support ......................................................................
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: David Hendricks david.hendricks@gmail.com --- M src/cpu/intel/Makefile.inc D src/cpu/intel/fsp_model_406dx/Kconfig D src/cpu/intel/fsp_model_406dx/Makefile.inc D src/cpu/intel/fsp_model_406dx/acpi.c D src/cpu/intel/fsp_model_406dx/bootblock.c D src/cpu/intel/fsp_model_406dx/chip.h D src/cpu/intel/fsp_model_406dx/model_406dx.h D src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/include/device/pci_ids.h D src/northbridge/intel/fsp_rangeley/Kconfig D src/northbridge/intel/fsp_rangeley/Makefile.inc D src/northbridge/intel/fsp_rangeley/acpi.c D src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl D src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl D src/northbridge/intel/fsp_rangeley/chip.h D src/northbridge/intel/fsp_rangeley/fsp/Kconfig D src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc D src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c D src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h D src/northbridge/intel/fsp_rangeley/memmap.c D src/northbridge/intel/fsp_rangeley/northbridge.c D src/northbridge/intel/fsp_rangeley/northbridge.h D src/northbridge/intel/fsp_rangeley/port_access.c M src/southbridge/intel/common/watchdog.c D src/southbridge/intel/fsp_rangeley/Kconfig D src/southbridge/intel/fsp_rangeley/Makefile.inc D src/southbridge/intel/fsp_rangeley/acpi.c D src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl D src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h D src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl D src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl D src/southbridge/intel/fsp_rangeley/acpi/lpc.asl D src/southbridge/intel/fsp_rangeley/acpi/pcie.asl D src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl D src/southbridge/intel/fsp_rangeley/acpi/sata.asl D src/southbridge/intel/fsp_rangeley/acpi/soc.asl D src/southbridge/intel/fsp_rangeley/acpi/usb.asl D src/southbridge/intel/fsp_rangeley/chip.h D src/southbridge/intel/fsp_rangeley/early_init.c D src/southbridge/intel/fsp_rangeley/early_smbus.c D src/southbridge/intel/fsp_rangeley/early_usb.c D src/southbridge/intel/fsp_rangeley/gpio.c D src/southbridge/intel/fsp_rangeley/gpio.h D src/southbridge/intel/fsp_rangeley/irq.h D src/southbridge/intel/fsp_rangeley/lpc.c D src/southbridge/intel/fsp_rangeley/nvs.h D src/southbridge/intel/fsp_rangeley/pci_devs.h D src/southbridge/intel/fsp_rangeley/romstage.c D src/southbridge/intel/fsp_rangeley/romstage.h D src/southbridge/intel/fsp_rangeley/sata.c D src/southbridge/intel/fsp_rangeley/smbus.c D src/southbridge/intel/fsp_rangeley/soc.c D src/southbridge/intel/fsp_rangeley/soc.h D src/southbridge/intel/fsp_rangeley/spi.c M src/vendorcode/intel/Kconfig D src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h D src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c D src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 68 files changed, 2 insertions(+), 9,280 deletions(-)
Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, but someone else must approve Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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David Hendricks (Code Review)
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HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)