[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control

[Subrata Banik (Code Review)]

Attention is currently required from: Eric Lai, Pranava Y N, Subrata Banik.

Hello Eric Lai, Kapil Porwal, Pranava Y N, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85934?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Code-Review+2 by Eric Lai, Code-Review+2 by Pranava Y N, Verified+1 by build bot (Jenkins)

Change subject: soc/intel/pantherlake: Refactor FSP log level control
......................................................................

soc/intel/pantherlake: Refactor FSP log level control

Refactor the FSP log level control by introducing a helper function
`fsp_set_debug_level()` to set the serial and MRC debug levels.

This change improves code readability and maintainability by separating
the log level setting logic from the main control flow. It also adds a
check to ensure the configured log levels are valid.

Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/romstage/fsp_params.c
1 file changed, 21 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85934/3