Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl 3 files changed, 160 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/1
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index f62780b..440d546 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,5 +47,16 @@ #include <ec/google/chromeec/acpi/ec.asl> }
+ /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/tigerlake_dev/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b9ed424..5b4801d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -144,6 +144,12 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "60" + register "Device4Enable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..46880d9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 85 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 75 +#define DPTF_CPU_ACTIVE_AC3 70 +#define DPTF_CPU_ACTIVE_AC4 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_TSR2_SENSOR_ID 1 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor 3" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 50 +#define DPTF_TSR2_ACTIVE_AC1 47 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + _SB.DPTF.TFN1, _SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 sensor */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 sensor */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +})
Hello build bot (Jenkins), Furquan Shaikh, caveh jalali, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#2).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
CQ-DEPEND=CL:39346 Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl 3 files changed, 160 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 54: variant/acpi/dptf.asl You need to add this under variant/ripto and variant/volteer and include baseboard/dptf.asl from there.
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 56: tigerlake_dev This is not correct.
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 151: Device4Enable This is not used by TGL SoC code. Also, what device is this?
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 138: 64000 Shouldn't this match what is in the devicetree?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 151: Device4Enable
This is not used by TGL SoC code. […]
This is for enabling TCPU as thermal zone.
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 138: 64000
Shouldn't this match what is in the devicetree?
Ack
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#4).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
CQ-DEPEND=CL:39346 Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl M src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl 5 files changed, 177 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 4:
(1 comment)
can you also create patch for TGLRVP?
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 151: Device4Enable
This is for enabling TCPU as thermal zone.
There is no fsp param setting in soc folder. src/soc/intel/tigerlake/fsp_params_tgl.c: You need to add fsp param setting to enable this.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 4:
Fix relation chain, soc patch should be first and mainboard patch is later for avoid compile error
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 4:
Patch Set 4:
(1 comment)
can you also create patch for TGLRVP?
Sure, will create patch once this volteer get merge. Currently, TGLRVP under WIP.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 151: Device4Enable
There is no fsp param setting in soc folder. […]
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 5:
Can you add Topic as TGL_UPSTREAM
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 54: variant/acpi/dptf.asl
You need to add this under variant/ripto and variant/volteer and include baseboard/dptf. […]
Done
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 56: tigerlake_dev
This is not correct.
Done
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 138: 64000
Ack
Done
https://review.coreboot.org/c/coreboot/+/39345/3/src/mainboard/google/voltee... PS3, Line 138: 64000
Ack
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/5/src/mainboard/google/voltee... PS5, Line 54: baseboard/acpi/dptf.asl This is still not correct. It should be variant/acpi/dptf.asl like you had before. What my earlier comment meant was you need to add dptf.asl file under variant/volteer and variant/ripto and those boards would include baseboard/acpi/dptf.asl. Please see hatch as example.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 5:
(1 comment)
Patch Set 5:
Can you add Topic as TGL_UPSTREAM
Done.
https://review.coreboot.org/c/coreboot/+/39345/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/5/src/mainboard/google/voltee... PS5, Line 54: baseboard/acpi/dptf.asl
This is still not correct. It should be variant/acpi/dptf.asl like you had before. […]
Ack
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 5:
Patch Set 5:
Can you add Topic as TGL_UPSTREAM
Done.
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Duncan Laurie, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#6).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
CQ-DEPEND=CL:39346 Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl 4 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/6
Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 6: Code-Review+1
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#7).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
CQ-DEPEND=CB:39346 Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl 4 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/7
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39345/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/39345/7/src/mainboard/google/voltee... PS7, Line 4: * Copyright (C) 2020 Intel Corporation. No dot at the end.
https://review.coreboot.org/c/coreboot/+/39345/7/src/mainboard/google/voltee... PS7, Line 42: #define DPTF_TSR1_ACTIVE_AC4 39 Use tabs consistently for alignment. Please be more careful of these things.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39345/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/39345/7/src/mainboard/google/voltee... PS7, Line 4: * Copyright (C) 2020 Intel Corporation.
No dot at the end.
Done
https://review.coreboot.org/c/coreboot/+/39345/7/src/mainboard/google/voltee... PS7, Line 42: #define DPTF_TSR1_ACTIVE_AC4 39
Use tabs consistently for alignment. Please be more careful of these things.
Done
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#8).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
CQ-DEPEND=CB:39346 Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl 4 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/8
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60 i realize PL1 is higher in the EDS, but this number is still a lot higher than PL1*1.25 in the EDS for UP3. how did you come up with 60w?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
i realize PL1 is higher in the EDS, but this number is still […]
This is as per the EDS document #607872.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
This is as per the EDS document #607872.
just chatted with the EEs, filed: https://issuetracker.google.com/issues/152639350 we need to have a closer look at these values in the context of the system design.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
just chatted with the EEs, filed: […]
Yes, sure. We have shared required info on this issue tracker. I agree with you on these particular values for system design.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
Yes, sure. We have shared required info on this issue tracker. […]
based on the discussion, it sounds like we need different PL2 values here depending on the CPU class used. a given variant could be built with either CPU, so this needs to be determined at boot time.
we did something similar for previous SoCs:
https://review.coreboot.org/c/coreboot/+/27765/ https://review.coreboot.org/27997 https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+...
does TGL have some ID regs we can use to decide which recommended PL2 value should be configured?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
based on the discussion, it sounds like we need different PL2 values […]
I think that's good reference based on board SKU id. BTW, what about PL4 setting? Don't we have code for setting PL4 According to partner bug we need to set up like below. https://partnerissuetracker.corp.google.com/issues/152639350#comment13
core L1 PL2 PL4 2c 15w 38w 71w 4c 15w 60w 105w
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
I think that's good reference based on board SKU id. […]
i'm actually hoping to avoid decoding the board SKU ID as there are going to be many combinations or encodings.
is there an intel CPU id we can use? looking at soc/intel/tigerlake/bootblock/report_platform.c maybe mchid can be use?
mch_table[] = { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, };
do these two map to 4c vs 2c? Tigerlake-U-4-2 Tigerlake-U-2-2
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
i'm actually hoping to avoid decoding the board SKU ID as […]
yes, these two U-4-2=4C and U-2-2=2C
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39345/8/src/mainboard/google/voltee... PS8, Line 168: 60
yes, these two U-4-2=4C and U-2-2=2C
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39345/8//COMMIT_MSG@16 PS8, Line 16: CQ-DEPEND=CB:39346 This syntax doesn't work, AFAIK. It's also not necessary, as long as there's a relation chain in gerrit, which you have done.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39345/8//COMMIT_MSG@16 PS8, Line 16: CQ-DEPEND=CB:39346
This syntax doesn't work, AFAIK. […]
Ack
Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Nick Vaccaro, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#10).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl 4 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/10
Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Nick Vaccaro, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#11).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl 6 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/11
Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Nick Vaccaro, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#14).
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
mb/google/volteer: Enable DPTF functionality
Enable DPTF functionality on volteer platform.
BRANCH=None BUG=b:149722146 TEST=Built and tested on Volteer system with these entries, cat /sys/class/thermal/thermal_zone*/type
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl 6 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/14
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 14:
Volteer proto2 SKU4 boots to the kernel with this patchset. How can I verify this does what it is supposed to do? "cat /sys/class/thermal/thermal_zone*/type" resulted in : x86_pkg_temp i2lwifi_1
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: mb/google/volteer: Enable DPTF functionality ......................................................................
Patch Set 14:
Patch Set 14:
Volteer proto2 SKU4 boots to the kernel with this patchset. How can I verify this does what it is supposed to do? "cat /sys/class/thermal/thermal_zone*/type" resulted in : x86_pkg_temp i2lwifi_1
I hope you have cherrypicked depenedncy patches. You should able to see the temperature changes as per load for all the thermal zones.
Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Nick Vaccaro, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#15).
Change subject: tigerlake: update processor power limits configuration ......................................................................
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None BUG=None TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl A src/soc/intel/common/acpi/dptf.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/systemagent.c 12 files changed, 248 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/15
Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Todd Broch, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#16).
Change subject: tigerlake: update processor power limits configuration ......................................................................
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None BUG=None TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl A src/soc/intel/common/acpi/dptf.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/systemagent.c 13 files changed, 217 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/16
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte... PS16, Line 55: /* Dynamic Platform Thermal Framework */ : Scope (_SB) : { : /* Per board variant specific definitions. */ : #include <variant/acpi/dptf.asl> : /* Include soc specific DPTF changes */ : #include <soc/intel/common/acpi/dptf.asl> : /* Include common dptf ASL files */ : #include <soc/intel/common/acpi/dptf/dptf.asl> : } This part should go in a separate change to enable DPTF on TGL.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte... PS16, Line 55: /* Dynamic Platform Thermal Framework */ : Scope (_SB) : { : /* Per board variant specific definitions. */ : #include <variant/acpi/dptf.asl> : /* Include soc specific DPTF changes */ : #include <soc/intel/common/acpi/dptf.asl> : /* Include common dptf ASL files */ : #include <soc/intel/common/acpi/dptf/dptf.asl> : }
This part should go in a separate change to enable DPTF on TGL.
Do you suggest that this part should be in other seperate patch to enable DPTF on volteer/tigerlake ? If I understand your comment correctly, we should device this whole patch into two seperate patches. Let me submit this way. patch: 1 -> for common code base processor power limits configuration changes patch: 2 -> for enablement of DPTF on TGL
Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Roy Mingi Park, Duncan Laurie, Todd Broch, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39345
to look at the new patch set (#17).
Change subject: tigerlake: update processor power limits configuration ......................................................................
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None BUG=None TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/systemagent.c 4 files changed, 18 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39345/17
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte... File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte... PS16, Line 55: /* Dynamic Platform Thermal Framework */ : Scope (_SB) : { : /* Per board variant specific definitions. */ : #include <variant/acpi/dptf.asl> : /* Include soc specific DPTF changes */ : #include <soc/intel/common/acpi/dptf.asl> : /* Include common dptf ASL files */ : #include <soc/intel/common/acpi/dptf/dptf.asl> : }
Do you suggest that this part should be in other seperate patch to enable DPTF on volteer/tigerlake […]
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
Patch Set 18: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
Patch Set 18: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None BUG=None TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/systemagent.c 4 files changed, 18 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..a55b543 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -53,6 +53,7 @@ select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a32cebe..2e3591f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/power_limit.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/gpio_defs.h> @@ -26,6 +27,9 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
+ /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -144,8 +148,7 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ uint8_t speed_shift_enable;
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index fb3441d..28dfb38 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -24,7 +24,4 @@ /* Common Timer Copy (CTC) frequency - 38.4MHz. */ #define CTC_FREQ 38400000
-/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 4cdca50..977c667 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -7,10 +7,13 @@ */
#include <device/device.h> +#include <delay.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h>
/* @@ -60,9 +63,18 @@ */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr();
/* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration ......................................................................
Patch Set 19:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3670 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3669 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3668 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3667
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Caveh Jalali (Code Review)
-
Furquan Shaikh (Code Review)
-
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Roy Mingi Park (Code Review)
-
Sumeet R Pawnikar (Code Review)
-
Tim Wawrzynczak (Code Review)
-
Wonkyu Kim (Code Review)