[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP

[Arthur Heymans (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
......................................................................

Patch Set 5: Code-Review+1

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81098/comment/5011cebb_812f1f60 :
PS5, Line 14: Additionally, the assumption of socket0/stack0 is a PCIe stack is not
            : always true for future generation SoCs and hence this assumption is
            : removed.
sidenote: This is still assumed in iio_pci_domain_read_resources.

Patchset:

PS5: 
Looks good to me, but I do have question on how to handle the statically created devicetree structure.

The domain for stack0 socket0 is created at buildtime via devicetree.cb or chipset.cb. Would it make sense to assert that this one gets matched with at least one of the domains?