Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34199 )
Change subject: intel/socket_mPGA604: Enable TSC_CONSTANT_RATE ......................................................................
intel/socket_mPGA604: Enable TSC_CONSTANT_RATE
We can use intel/common implementation for tsc_freq_mhz().
Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/socket_mPGA604/Kconfig 2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/34199/1
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 9bb5dca..5d60d21 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,5 @@ +subdirs-y += ../common + ramstage-y += model_f2x_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 1453f99..4ec46e0 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,9 +9,12 @@ select MMX select SSE select UDELAY_TSC + select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34199 )
Change subject: intel/socket_mPGA604: Enable TSC_CONSTANT_RATE ......................................................................
Patch Set 6: Code-Review+2
looks reasonable enough, but I don't have the gear to test it.
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34199 )
Change subject: intel/socket_mPGA604: Enable TSC_CONSTANT_RATE ......................................................................
intel/socket_mPGA604: Enable TSC_CONSTANT_RATE
We can use intel/common implementation for tsc_freq_mhz().
Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199 Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/socket_mPGA604/Kconfig 2 files changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 9bb5dca..5d60d21 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,5 @@ +subdirs-y += ../common + ramstage-y += model_f2x_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 1453f99..4ec46e0 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,9 +9,12 @@ select MMX select SSE select UDELAY_TSC + select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on
-
Kyösti Mälkki (Code Review) -
Patrick Georgi (Code Review)