Change in coreboot[master]: soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data training

[Moritz Fischer (Code Review)]

Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50886 )

Change subject: soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data training
......................................................................

soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data training

Clear PI_175 interrupts before attempting training in all relevant
calls.

Signed-off-by: Moritz Fischer 
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
---
M src/soc/rockchip/rk3399/sdram.c
1 file changed, 21 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50886/1

diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 132759a..89463aa 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -618,6 +618,9 @@
    u32 obs_0, obs_1, obs_2, obs_err = 0;
    u32 rank = params->ch[channel].rank;

+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	write32(&denali_pi[175], 0x00003f7c);
+
    for (i = 0; i < rank; i++) {
    	select_per_cs_training_index(channel, i);
    	/* PI_100 PI_CALVL_EN:RW:8:2 */
@@ -647,7 +650,7 @@
    			return -1;
    	}
    	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
-		write32((&denali_pi[175]), 0x00003f7c);
+		write32(&denali_pi[175], 0x00003f7c);
    }
    clrbits32(&denali_pi[100], 0x3 << 8);

@@ -662,6 +665,9 @@
    u32 rank = params->ch[channel].rank;
    u32 i, tmp;

+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	write32(&denali_pi[175], 0x00003f7c);
+
    for (i = 0; i < rank; i++) {
    	select_per_cs_training_index(channel, i);
    	/* PI_60 PI_WRLVL_EN:RW:8:2 */
@@ -692,7 +698,7 @@
    			return -1;
    	}
    	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
-		write32((&denali_pi[175]), 0x00003f7c);
+		write32(&denali_pi[175], 0x00003f7c);
    }

override_write_leveling_value(channel);
@@ -731,6 +737,10 @@
    	clrbits32(&denali_phy[262], 0x7 << 24);
    	clrbits32(&denali_phy[390], 0x7 << 24);
    }
+
+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	write32(&denali_pi[175], 0x00003f7c);
+
    for (i = 0; i < rank; i++) {
    	select_per_cs_training_index(channel, i);
    	/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
@@ -765,7 +775,7 @@
    			return -1;
    	}
    	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
-		write32((&denali_pi[175]), 0x00003f7c);
+		write32(&denali_pi[175], 0x00003f7c);
    }
    clrbits32(&denali_pi[80], 0x3 << 24);

@@ -790,6 +800,9 @@

u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;

+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	write32(&denali_pi[175], 0x00003f7c);
+
    for (i = 0; i < rank; i++) {
    	select_per_cs_training_index(channel, i);
    	/* PI_80 PI_RDLVL_EN:RW:16:2 */
@@ -813,7 +826,7 @@
    			return -1;
    	}
    	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
-		write32((&denali_pi[175]), 0x00003f7c);
+		write32(&denali_pi[175], 0x00003f7c);
    }
    clrbits32(&denali_pi[80], 0x3 << 16);

@@ -826,6 +839,9 @@
    u32 rank = params->ch[channel].rank;
    u32 i, tmp;

+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	write32(&denali_pi[175], 0x00003f7c);
+
    for (i = 0; i < rank; i++) {
    	select_per_cs_training_index(channel, i);
    	/*
@@ -848,7 +864,7 @@
    			return -1;
    	}
    	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
-		write32((&denali_pi[175]), 0x00003f7c);
+		write32(&denali_pi[175], 0x00003f7c);
    }
    clrbits32(&denali_pi[124], 0x3 << 16);