[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports

[Sean Rhodes (Code Review)]

Attention is currently required from: Subrata Banik.

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email )

Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
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Patch Set 6:

(1 comment)

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/85696/comment/1dce51a1_a6bdfa40?usp... :
PS5, Line 437: 	if (rp_type != PCIE_RP_PCH) {
> earlier code was applicable for both CPU RPs as well but your patch looks like limiting it to only u […]

Sorry, bad commit msg!

I haven't found any docs for it - I just noticed that AMI has it, compared that to SBL that has it, so assumed coreboot was just "wrong".

Added in `32f883e53275320f5b023bc9027da0db127874b8`, but I can't tell why...