Change in coreboot[master]: google/link: fix detection of dimm on channel 1

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

google/link: fix detection of dimm on channel 1

Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/link/romstage.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35084/1

diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 2f3f07c..1fe71ea 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -156,8 +156,12 @@
    	},
    };
    *pei_data = pei_data_template;
+	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
+	   both need to be populated */
    memcpy(pei_data->spd_data[0], locate_spd(),
           sizeof(pei_data->spd_data[0]));
+	memcpy(pei_data->spd_data[2], pei_data->spd_data[0],
+	       sizeof(pei_data->spd_data[0]));
 }

const struct southbridge_usb_port mainboard_usb_ports[] = {

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

Patch Set 1: Code-Review+2

Line length is now 96 chars, so I think some of the lines would fit completely.

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

Patch Set 1: Code-Review-1

(1 comment)

https://review.coreboot.org/c/coreboot/+/35084/1/src/mainboard/google/link/r... 
File src/mainboard/google/link/romstage.c:

https://review.coreboot.org/c/coreboot/+/35084/1/src/mainboard/google/link/r... 
PS1, Line 187: locate_spd
Please fix native raminit DIMM detection as well

[Matt DeVillier (Code Review)]

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35084

to look at the new patch set (#2).

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

google/link: fix detection of dimm on channel 1

Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/link/romstage.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35084/2

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35084/1/src/mainboard/google/link/r... 
File src/mainboard/google/link/romstage.c:

https://review.coreboot.org/c/coreboot/+/35084/1/src/mainboard/google/link/r... 
PS1, Line 187: locate_spd
> Please fix native raminit DIMM detection as well

Done

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

Patch Set 2: Code-Review+1

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

google/link: fix detection of dimm on channel 1

Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) 
Reviewed-by: Kyösti Mälkki 
Reviewed-by: Patrick Rudolph 
---
M src/mainboard/google/link/romstage.c
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, but someone else must approve
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 2f3f07c..8e8d943 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -156,8 +156,12 @@
    	},
    };
    *pei_data = pei_data_template;
+	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
+	   both need to be populated */
    memcpy(pei_data->spd_data[0], locate_spd(),
           sizeof(pei_data->spd_data[0]));
+	memcpy(pei_data->spd_data[2], pei_data->spd_data[0],
+	       sizeof(pei_data->spd_data[0]));
 }

const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -180,7 +184,10 @@

void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
+	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
+	   both need to be populated */
    memcpy(&spd[0], locate_spd(), 128);
+	memcpy(&spd[2], &spd[0], 128);
 }

void mainboard_early_init(int s3resume)