[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85561?usp=email

to look at the new patch set (#4).

Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER
......................................................................

soc/intel/xeon_sp: Allow OS to control LTR and AER

There's no reason to tell the OS to disable LTR. On UEFI and
on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP.

There's no SMM (RAS) code that is able to parse AER structures,
thus let the OS always control AER. On coreboot's GNR AER is
also always granted to the OS.

TEST: Run code on ocp/tiogapass and observed dmesg:
      The OS now prints:
acpi PNP0A08:04: _OSC: OS now controls [PME PCIeCapability LTR]

Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85561/4