Attention is currently required from: Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55200 )
Change subject: cpu/x86/lapic: Avoid aliasing MMIO writes ......................................................................
Patch Set 11:
(1 comment)
File src/include/cpu/x86/lapic.h:
https://review.coreboot.org/c/coreboot/+/55200/comment/43cba68e_0c2cdfc8 PS11, Line 16: 0x400 SDM Vol 3A section 10.4.1 (The Local APIC Block Diagram) says the following:
APIC registers are memory-mapped to a 4-KByte region of the processor’s physical address space with an initial starting address of FEE00000H.
If I understand it correctly, shouldn't this array be 4 KiB in size? Or is this just 1 KiB because it covers all the defined registers?
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Angel Pons (Code Review)