Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/1
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..fc5c7bd 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -57,6 +57,11 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_by_index = true, + .spd_spec.spd_index = variant_memory_sku(), + }; + wilco_ec_romstage_init();
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ff0240c..c20c6ff 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -234,6 +234,11 @@ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), +/* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F14, NONE, PLTRST), +/* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F15, NONE, PLTRST), +/* PCH_MEM_STRAP4 */ PAD_CFG_GPI(GPP_F16, NONE, PLTRST), };
/* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index ca54580..51287d4 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -25,4 +25,7 @@ /* Return memory SKU for the variant */ int variant_memory_sku(void);
-#endif +/* Return board specific memory configuration */ +const struct cnl_mb_cfg *variant_memory_params(void); + +#endif /* VARIANT_H */ diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 2a1d8d9..25cab04 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -17,6 +17,35 @@ #include <gpio.h> #include <variant/gpio.h>
+static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 120, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 120, 81, 100 }, + + /* Baseboard Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, +}; + +const struct cnl_mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + int variant_memory_sku(void) { gpio_t spd_gpios[] = {
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#2).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration(still need spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 181 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/2/src/mainboard/google/dralli... PS2, Line 69: switch(val) { space required before the open parenthesis '('
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#3).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration(still need spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 181 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 69: switch(val) { space required before the open parenthesis '('
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/2/src/mainboard/google/dralli... PS2, Line 69: switch(val) {
space required before the open parenthesis '('
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 21: /* Access memory info through SMBUS. */ : .spd[0] = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address = 0xa0}, : }, : .spd[1] = {.read_type = NOT_EXISTING}, : .spd[2] = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address = 0xa4}, : }, : .spd[3] = {.read_type = NOT_EXISTING}, not needed, since you are passing the spd.bin
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 20: ## ToDo
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 21: consistent spacing as above.
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 180: /* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), : /* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), : /* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), : /* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), : /* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), change this rather.
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 49: int variant_memory_sku duplicate funcṭion, you have it defined in romstage.c already
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 70: case 17: : val = 0; : break; : case 18: : val = 2; : break; : case 19: : case 20: : val = 0; : break; : case 25: : val = 2; : break; : case 26: : val = 3; : break; : } case 27: : val = 2; : break; : case 28: : val = 1; : break; : } club similar cases.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 49: int variant_memory_sku
duplicate funcṭion, you have it defined in romstage. […]
sorry,memory.c
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 69: switch(val) { We will have SPD file for each memory. We don't share the SPD, we need part number for each, We don't have CBI to fill that.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 237: /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), Should we put this into early init table? We need this in ROM stage.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 21: /* Access memory info through SMBUS. */ : .spd[0] = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address = 0xa0}, : }, : .spd[1] = {.read_type = NOT_EXISTING}, : .spd[2] = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address = 0xa4}, : }, : .spd[3] = {.read_type = NOT_EXISTING},
not needed, since you are passing the spd. […]
We should change to read by CBFS, right?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35141/3//COMMIT_MSG@15 PS3, Line 15: 3. Include spd configuration(still need spd for 16G_3200.spd.hex to complete) Please add a space before (.
https://review.coreboot.org/c/coreboot/+/35141/3//COMMIT_MSG@15 PS3, Line 15: need needs
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#4).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 181 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 4:
(10 comments)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 180: /*_PCH_MEM_STRAP0_*/ PAD_CFG_GPI(GPP_F12,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 180: /*_PCH_MEM_STRAP0_*/ PAD_CFG_GPI(GPP_F12,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 181: /*_PCH_MEM_STRAP1_*/ PAD_CFG_GPI(GPP_F13,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 181: /*_PCH_MEM_STRAP1_*/ PAD_CFG_GPI(GPP_F13,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 182: /*_PCH_MEM_STRAP2_*/ PAD_CFG_GPI(GPP_F14,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 182: /*_PCH_MEM_STRAP2_*/ PAD_CFG_GPI(GPP_F14,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 183: /*_PCH_MEM_STRAP3_*/ PAD_CFG_GPI(GPP_F15,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 183: /*_PCH_MEM_STRAP3_*/ PAD_CFG_GPI(GPP_F15,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 184: /*_PCH_MEM_STRAP4_*/ PAD_CFG_GPI(GPP_F16,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 184: /*_PCH_MEM_STRAP4_*/ PAD_CFG_GPI(GPP_F16,_NONE,_PLTRST), space required after that ',' (ctx:VxV)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#5).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 181 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/5
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/c/coreboot/+/35141/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35141/3//COMMIT_MSG@15 PS3, Line 15: 3. Include spd configuration(still need spd for 16G_3200.spd.hex to complete)
Please add a space before (.
Done
https://review.coreboot.org/c/coreboot/+/35141/3//COMMIT_MSG@15 PS3, Line 15: need
needs
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 21: /* Access memory info through SMBUS. */ : .spd[0] = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address = 0xa0}, : }, : .spd[1] = {.read_type = NOT_EXISTING}, : .spd[2] = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address = 0xa4}, : }, : .spd[3] = {.read_type = NOT_EXISTING},
We should change to read by CBFS, right?
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 20: ##
ToDo
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 21:
consistent spacing as above.
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 180: /* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), : /* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), : /* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), : /* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), : /* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE),
change this rather.
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 49: int variant_memory_sku
sorry,memory. […]
So, There is no duplicate right. This function is defined only in memory.c file.
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 70: case 17: : val = 0; : break; : case 18: : val = 2; : break; : case 19: : case 20: : val = 0; : break; : case 25: : val = 2; : break; : case 26: : val = 3; : break; : } case 27: : val = 2; : break; : case 28: : val = 1; : break; : }
club similar cases.
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 237: /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
Should we put this into early init table? We need this in ROM stage.
Agree, Please move to early gpio table.
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 49: int variant_memory_sku
So, There is no duplicate right. This function is defined only in memory.c file.
No. This is fine.
Chiranjeevi Rapolu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 18: 3200 3200 is a mistake. Can you limit the speed to 2666MHz?
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 22: 11 What about other memory configurations? Are you combining same speed grades into one?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#6).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 181 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/6
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 18: 3200
3200 is a mistake. […]
Let me confirm with Tim about exact speed, before I make further changes.
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 22: 11
What about other memory configurations? Are you combining same speed grades into one?
Yes, I am combining same speed grades in to one, as we use generic spd.hex for 8GB and 16GB DDR4 based on their corresponding speeds.
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 237: /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
Agree, Please move to early gpio table.
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 22: 11
Yes, I am combining same speed grades in to one, as we use generic spd. […]
Please notice we need SPD file for each DDR module. We don't share generic SPD file. This is for customer request.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 69: switch (val) { CONFIG0=F12 indicates High bit, could you check with memory config table?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... PS6, Line 49: .spd_by_index = true, memcfg.spd[0].read_type = READ_SPD_CBFS; should we need this???
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... PS6, Line 232: /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), Duplicate, we can remove this. Already configure in early table.
Chiranjeevi Rapolu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
Patch Set 6:
(1 comment)
I agree. We need to have separate timings programmed per respective DDR part rather than generalizing them. Generalizing may result non-optimal timings for the DDR, stability/performance will suffer.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
Patch Set 6:
Patch Set 6:
(1 comment)
I agree. We need to have separate timings programmed per respective DDR part rather than generalizing them. Generalizing may result non-optimal timings for the DDR, stability/performance will suffer.
Please wait, our BIOS team asking vendor for that now. we can track SPD file in the issue tracker.
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(10 comments)
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 180: /*_PCH_MEM_STRAP0_*/ PAD_CFG_GPI(GPP_F12,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 180: /*_PCH_MEM_STRAP0_*/ PAD_CFG_GPI(GPP_F12,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 181: /*_PCH_MEM_STRAP1_*/ PAD_CFG_GPI(GPP_F13,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 181: /*_PCH_MEM_STRAP1_*/ PAD_CFG_GPI(GPP_F13,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 182: /*_PCH_MEM_STRAP2_*/ PAD_CFG_GPI(GPP_F14,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 182: /*_PCH_MEM_STRAP2_*/ PAD_CFG_GPI(GPP_F14,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 183: /*_PCH_MEM_STRAP3_*/ PAD_CFG_GPI(GPP_F15,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 183: /*_PCH_MEM_STRAP3_*/ PAD_CFG_GPI(GPP_F15,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 184: /*_PCH_MEM_STRAP4_*/ PAD_CFG_GPI(GPP_F16,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35141/4/src/mainboard/google/dralli... PS4, Line 184: /*_PCH_MEM_STRAP4_*/ PAD_CFG_GPI(GPP_F16,_NONE,_PLTRST),
space required after that ',' (ctx:VxV)
Done
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 22: 11
Please notice we need SPD file for each DDR module. We don't share generic SPD file. […]
Ack
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#7).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 176 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/7
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... PS6, Line 232: /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
Duplicate, we can remove this. Already configure in early table.
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 69: switch (val) {
CONFIG0=F12 indicates High bit, could you check with memory config table?
Sorry, please ignore this. CONFIG_0 is bit 0.
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 69: switch (val) {
Sorry, please ignore this. CONFIG_0 is bit 0.
Ack
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Thejaswani Putta,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#8).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 188 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/8/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/8/src/mainboard/google/dralli... PS8, Line 59: for(int i = 0; i < 3; i = i+2) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/35141/8/src/mainboard/google/dralli... PS8, Line 59: for(int i = 0; i < 3; i = i+2) space required before the open parenthesis '('
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#9).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 187 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/9/src/mainboard/google/dralli... PS9, Line 59: for (int i = 0; i < 3; i = i+2){ space required before the open brace '{'
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#10).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 187 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/10
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 10:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/6/src/mainboard/google/dralli... PS6, Line 49: .spd_by_index = true,
memcfg.spd[0]. […]
Done
https://review.coreboot.org/c/coreboot/+/35141/8/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/8/src/mainboard/google/dralli... PS8, Line 59: for(int i = 0; i < 3; i = i+2)
that open brace { should be on the previous line
Done
https://review.coreboot.org/c/coreboot/+/35141/8/src/mainboard/google/dralli... PS8, Line 59: for(int i = 0; i < 3; i = i+2)
space required before the open parenthesis '('
Done
https://review.coreboot.org/c/coreboot/+/35141/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/9/src/mainboard/google/dralli... PS9, Line 59: for (int i = 0; i < 3; i = i+2){
space required before the open brace '{'
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 60: memcfg.spd[0].read_type = READ_SPD_CBFS; spd[i]?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 251: /*_PCH_MEM_STRAP0_*/ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), We done this in GPIO update CL. you can remove this.https://review.coreboot.org/c/coreboot/+/35175
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 59: int val = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); I think this change is needn't. We will upload SPD for each within few days.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 17: SPD_SOURCES = 8G_2666 # 0b00000 We will update the SPD. We update this in another CL.
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#11).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 187 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/11
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 60: memcfg.spd[0].read_type = READ_SPD_CBFS;
spd[i]?
Done
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#12).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/spd/16G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_2666.spd.hex A src/mainboard/google/drallion/spd/8G_3200.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 8 files changed, 152 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/12
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 12:
Patch Set 10:
(1 comment)
Removed,After this patch: https://review.coreboot.org/c/coreboot/+/35346 Thanks.
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#13).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 5 files changed, 56 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/13
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#14).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 5 files changed, 51 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/14
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#15).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 5 files changed, 56 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/15
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#16).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 51 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/16
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#17).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include spd configuration (still needs spd for 16G_3200.spd.hex to complete)
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 49 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/17
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 251: /*_PCH_MEM_STRAP0_*/ PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
We done this in GPIO update CL. you can remove this.https://review.coreboot. […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... PS17, Line 48: struct cnl_mb_cfg memcfg; We should guard CONFIG_DRALLION here.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... PS17, Line 21: /* Access memory info through SMBUS. */ We should keep this if you want keep support sarien/arcada cml for a while.
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#18).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 49 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/18
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... PS17, Line 21: /* Access memory info through SMBUS. */
We should keep this if you want keep support sarien/arcada cml for a while.
@Selma, Could you please comment on what would be the plan?
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#19).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 50 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/19
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... PS17, Line 21: /* Access memory info through SMBUS. */
@Selma, Could you please comment on what would be the plan?
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... PS19, Line 62: int mem_sku; You should guard this section or it will overwrite the sarien/arcada setting. You can put this into memory.c since you have variant_memory_params.
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... PS19, Line 62: int mem_sku;
You should guard this section or it will overwrite the sarien/arcada setting. […]
Yes, Agreed. I need to rebase my patch on top of Bernardo's - mb/google/drallion: Enable 360 sensor detection patch. Will update now.
Hello build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#20).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 47 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/20
Selma Bensaid has uploaded a new patch set (#22) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 47 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/22
Hello Selma Bensaid, build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#23).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 48 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/23
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/23/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/35141/23/src/mainboard/google/drall... PS23, Line 24: const_struct_cnl_mb_cfg_*variant_memory_params(void); "foo*bar" should be "foo *bar"
Hello Selma Bensaid, build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#24).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 48 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/24
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/23/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/35141/23/src/mainboard/google/drall... PS23, Line 24: const_struct_cnl_mb_cfg_*variant_memory_params(void);
"foo*bar" should be "foo *bar"
Fixed!
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... PS19, Line 62: int mem_sku;
Yes, Agreed. […]
Done!
Hello Selma Bensaid, build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#25).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 54 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/25
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 25:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... PS25, Line 23: const struct cnl_mb_cfg *__weak_variant_memory_params(void) You can pass the memcfg and return it directly. weak_variant_memory_params(struct cnl_mb_cfg memcfg) { return mem_cfg; }
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... PS25, Line 29: static const struct cnl_mb_cfg memcfg = { Remove static const here, because we want to override it.
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... PS25, Line 70: variant_memory_params(); Nothing happens here. You should pass the memcfg for override it. variant_memory_params(memcfg);
Selma Bensaid has uploaded a new patch set (#26) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 56 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/26
Selma Bensaid has uploaded a new patch set (#27) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 56 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/27
Selma Bensaid has uploaded a new patch set (#28) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 56 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/28
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... PS28, Line 63: const struct cnl_mb_cfg *__weak get_variant_memory_cfg(void) miss declare in header file. src/mainboard/google/drallion/romstage.c:63:33: error: no previous prototype for 'get_variant_memory_cfg' [-Werror=missing-prototypes] const struct cnl_mb_cfg *__weak get_variant_memory_cfg(void)
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/include/variant/variant.h:
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... PS28, Line 28: #endif /* VARIANT_H */ you can drop this
Selma Bensaid has uploaded a new patch set (#29) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 56 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/29
Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 29:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... PS25, Line 23: const struct cnl_mb_cfg *__weak_variant_memory_params(void)
You can pass the memcfg and return it directly. […]
Ack
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... PS25, Line 70: variant_memory_params();
Nothing happens here. You should pass the memcfg for override it. […]
Ack
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... PS28, Line 63: const struct cnl_mb_cfg *__weak get_variant_memory_cfg(void)
miss declare in header file. […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 29:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/29/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/29/src/mainboard/google/drall... PS29, Line 28: static const struct cnl_mb_cfg baseboard_memcfg = { #include <soc/cnl_memcfg_init.h>, for fix build error.invalid use of undefined type 'const struct cnl_mb_cfg'
Selma Bensaid has uploaded a new patch set (#30) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 57 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/30
Selma Bensaid has uploaded a new patch set (#31) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 58 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/31
Selma Bensaid has uploaded a new patch set (#32) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 58 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/32
Selma Bensaid has uploaded a new patch set (#33) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 39 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/33
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 33:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/33/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/33/src/mainboard/google/drall... PS33, Line 62: const struct cnl_mb_cfg *__weak get_variant_memory_cfg(cnl_mb_cfg *mem_cfg) { need consistent spacing around '*' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/35141/33/src/mainboard/google/drall... PS33, Line 63: return(&memcfg); return is not a function, parentheses are not required
Selma Bensaid has uploaded a new patch set (#34) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 39 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/34
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... PS34, Line 62: const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) { open brace '{' following function definitions go on the next line
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... PS34, Line 68: struct cnl_mb_cfg memcfg board_memcfg; remove memcfg here, you only use board_memcfg
Selma Bensaid has uploaded a new patch set (#35) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/35
Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 35:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... PS34, Line 62: const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) {
open brace '{' following function definitions go on the next line
Done
https://review.coreboot.org/c/coreboot/+/35141/34/src/mainboard/google/drall... PS34, Line 68: struct cnl_mb_cfg memcfg board_memcfg;
remove memcfg here, you only use board_memcfg
Done
https://review.coreboot.org/c/coreboot/+/35141/29/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/29/src/mainboard/google/drall... PS29, Line 28: static const struct cnl_mb_cfg baseboard_memcfg = {
#include <soc/cnl_memcfg_init.h>, for fix build error. […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 35:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... PS35, Line 36: mem_cfg->rcomp_resistor = { 120, 81, 100 }; rcomp_resistor[]
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... PS35, Line 37: mem_cfg->rcomp_targets = { 100, 40, 20, 20, 26 }; rcomp_targets[]
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... PS35, Line 39: mem_cfg->.ect = 1; mem_cfg->ect
Selma Bensaid has uploaded a new patch set (#36) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/36
Selma Bensaid has uploaded a new patch set (#37) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/37
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 37:
Patch Set 35:
(3 comments)
Sorry, we can assign by [] = {} beside declaration;
Selma Bensaid has uploaded a new patch set (#38) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/38
Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 38:
Patch Set 37:
Patch Set 35:
(3 comments)
Sorry, we can assign by [] = {} beside declaration;
:) I'm using memcpy, I think it's better
Selma Bensaid has uploaded a new patch set (#39) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 59 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/39
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 37:
Patch Set 37:
Patch Set 35:
(3 comments)
Sorry, we can assign by [] = {} beside declaration;
typo can't
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 39:
Patch Set 38:
Patch Set 37:
Patch Set 35:
(3 comments)
Sorry, we can assign by [] = {} beside declaration;
:) I'm using memcpy, I think it's better
Agree! We are close to finish this hard working.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 39:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/39/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/39/src/mainboard/google/drall... PS39, Line 58: memcpy(mem_cfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); need string.h
Selma Bensaid has uploaded a new patch set (#40) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 59 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/40
Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 40:
(1 comment)
Patch Set 39:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35141/39/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/39/src/mainboard/google/drall... PS39, Line 58: memcpy(mem_cfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
need string. […]
Done
Selma Bensaid has uploaded a new patch set (#41) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 60 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/41
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 41: Code-Review+1
Selma Bensaid has uploaded a new patch set (#42) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/42
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 42:
@Selma, this conflict is compare to the master. But in the relation chain, it's fine. I think you don't need to rebase but wait the CL get merged.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 42:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... PS42, Line 24: nit:remove the wrap line
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... PS42, Line 61: /*_In_Drallion_dual_channel_is_enabled_by_default. nit:Comment here is space or under line?
Hello EricR Lai, Selma Bensaid, build bot (Jenkins), Thejaswani Putta, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35141
to look at the new patch set (#43).
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 58 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/43
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 43:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... PS42, Line 24:
nit:remove the wrap line
Done
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/42/src/mainboard/google/drall... PS42, Line 61: /*_In_Drallion_dual_channel_is_enabled_by_default.
nit:Comment here is space or under line?
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 43: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 43:
(12 comments)
Please remember to mark comments as "resolved" once they're handled, otherwise the change isn't ready for submit.
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/17/src/mainboard/google/drall... PS17, Line 48: struct cnl_mb_cfg memcfg;
We should guard CONFIG_DRALLION here.
Done
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/19/src/mainboard/google/drall... PS19, Line 62: int mem_sku;
Done!
Done
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/35141/25/src/mainboard/google/drall... PS25, Line 29: static const struct cnl_mb_cfg memcfg = {
Remove static const here, because we want to override it.
Now done through the weak get_variant_memory_cfg() function.
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/5/src/mainboard/google/dralli... PS5, Line 18: 3200
Let me confirm with Tim about exact speed, before I make further changes.
The entire scheme changed, so closing
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 17: SPD_SOURCES = 8G_2666 # 0b00000
We will update the SPD. We update this in another CL.
Done
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/include/variant/variant.h:
https://review.coreboot.org/c/coreboot/+/35141/28/src/mainboard/google/drall... PS28, Line 28: #endif /* VARIANT_H */
you can drop this
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 49: int variant_memory_sku
No. This is fine.
Done
https://review.coreboot.org/c/coreboot/+/35141/3/src/mainboard/google/dralli... PS3, Line 69: switch(val) {
We will have SPD file for each memory. […]
Done
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/10/src/mainboard/google/drall... PS10, Line 59: int val = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
I think this change is needn't. We will upload SPD for each within few days.
Done
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... PS35, Line 36: mem_cfg->rcomp_resistor = { 120, 81, 100 };
rcomp_resistor[]
Ack
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... PS35, Line 37: mem_cfg->rcomp_targets = { 100, 40, 20, 20, 26 };
rcomp_targets[]
Ack
https://review.coreboot.org/c/coreboot/+/35141/35/src/mainboard/google/drall... PS35, Line 39: mem_cfg->.ect = 1;
mem_cfg->ect
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 58 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index c9f009e..03bc17f 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -58,11 +58,18 @@ .vref_ca_config = 2, };
+const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + return &memcfg; +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct cnl_mb_cfg board_memcfg; + variant_mainboard_post_init_params(memupd);
wilco_ec_romstage_init();
- cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + cannonlake_memcfg_init(&memupd->FspmConfig, get_variant_memory_cfg(&board_memcfg)); } diff --git a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h index 1edd660..eb1d9ae 100644 --- a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h @@ -17,7 +17,11 @@ #define BASEBOARD_VARIANTS_H
#include <fsp/api.h> +#include <soc/cnl_memcfg_init.h>
void variant_mainboard_post_init_params(FSPM_UPD *mupd);
+/* Return board specific memory configuration */ +const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index c837805..10996a3 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -16,6 +16,8 @@ #include <variant/variant.h> #include <gpio.h> #include <variant/gpio.h> +#include <baseboard/variants.h> +#include <string.h>
/* Use spd_index array to save mem_id */ static const int spd_index[32] = { @@ -25,6 +27,50 @@ 5, 0, 7, 2, 0, 0, 0, 0 };
+const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + int mem_sku; + struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 120, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 120, 81, 100 }, + + /* Baseboard Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + }; + + mem_sku = variant_memory_sku(); + + memcpy(mem_cfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); + + /* In Drallion dual channel is enabled by default. + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, Ch1D1 respectively. + * Dual-DIMM memory is not used in drallion family, so we only + * fill in spd info for CH0D0 and CH1D0 here. + */ + for (int i = 0; i < 3; i = i+2) { + mem_cfg->spd[i].read_type = READ_SPD_CBFS; + mem_cfg->spd[i].spd_spec.spd_index = mem_sku; + } + + return mem_cfg; +} + int variant_memory_sku(void) { gpio_t spd_gpios[] = {
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
Patch Set 44:
Patch Set 43:
(12 comments)
Please remember to mark comments as "resolved" once they're handled, otherwise the change isn't ready for submit.
Sure, I will. Thanks!
-
Aamir Bohra (Code Review) -
build bot (Jenkins) (Code Review)
-
Chiranjeevi Rapolu (Code Review)
-
EricR Lai (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
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Selma Bensaid (Code Review)
-
Thejaswani Putta (Code Review)