Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 )

Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
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Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/r... 
File src/soc/intel/xeon_sp/cpx/romstage.c:

https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/r... 
PS4, Line 79: 0x1a
> actKeyByte2 is SPD Byte 3: Module type information for SPD_RDIMM, SPD_UDIMM, SPD_SODIMM., etc.

Ack

https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/r... 
PS4, Line 88: 1200
> Yes you are right, but CPX does not support DDR5 and DDR4 should be the only option in use, I am not […]

If the HOB provides this information, why not use it?