EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37691 )
Change subject: mb/google/hatch: Update GCPM method from SoC ......................................................................
mb/google/hatch: Update GCPM method from SoC
Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 --- M src/mainboard/google/hatch/mainboard.asl 1 file changed, 2 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37691/1
diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl index dff1a75..78129d0 100644 --- a/src/mainboard/google/hatch/mainboard.asl +++ b/src/mainboard/google/hatch/mainboard.asl @@ -15,21 +15,13 @@
#include <intelblocks/gpio.h>
-Method (LOCL, 1, Serialized) -{ - For (Local0 = 0, Local0 < 5, Local0++) - { - _SB.PCI0.CGPM (Local0, Arg0) - } -} - /* * Method called from _PTS prior to system sleep state entry * Enables dynamic clock gating for all 5 GPIO communities */ Method (MPTS, 1, Serialized) { - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + _SB.PCI0.GCPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) }
/* @@ -38,20 +30,5 @@ */ Method (MWAK, 1, Serialized) { - LOCL (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from _SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - LOCL (0) - } + _SB.PCI0.GCPM (0) }
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37691 )
Change subject: mb/google/hatch: Update GCPM method from SoC ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37691/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/37691/1/src/mainboard/google/hatch/... PS1, Line 24: _SB.PCI0.GCPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) If we decide to make this common, should we move this to SOC level as well?
Hello Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37691
to look at the new patch set (#2).
Change subject: mb/google/hatch: Update GCPM method from SoC ......................................................................
mb/google/hatch: Update GCPM method from SoC
Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 --- M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/mainboard.asl 2 files changed, 0 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37691/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37691 )
Change subject: mb/google/hatch: Update GCPM method from SoC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37691/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/37691/1/src/mainboard/google/hatch/... PS1, Line 24: _SB.PCI0.GCPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
If we decide to make this common, should we move this to SOC level as well?
Ack
Hello Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37691
to look at the new patch set (#3).
Change subject: mb/google/hatch: Update GCPM method from SoC ......................................................................
mb/google/hatch: Update GCPM method from SoC
Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 --- M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/mainboard.asl 2 files changed, 0 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37691/3
Hello Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37691
to look at the new patch set (#4).
Change subject: mb/google/hatch: Clean up duplicate method ......................................................................
mb/google/hatch: Clean up duplicate method
Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 --- M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/mainboard.asl 2 files changed, 0 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37691/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37691 )
Change subject: mb/google/hatch: Clean up duplicate method ......................................................................
Patch Set 4: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37691 )
Change subject: mb/google/hatch: Clean up duplicate method ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37691 )
Change subject: mb/google/hatch: Clean up duplicate method ......................................................................
mb/google/hatch: Clean up duplicate method
Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/mainboard.asl 2 files changed, 0 insertions(+), 60 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1e7f760..8807191 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -40,9 +40,6 @@ #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } - - /* Mainboard hooks */ - #include "mainboard.asl" }
#if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl deleted file mode 100644 index dff1a75..0000000 --- a/src/mainboard/google/hatch/mainboard.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Google, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <intelblocks/gpio.h> - -Method (LOCL, 1, Serialized) -{ - For (Local0 = 0, Local0 < 5, Local0++) - { - _SB.PCI0.CGPM (Local0, Arg0) - } -} - -/* - * Method called from _PTS prior to system sleep state entry - * Enables dynamic clock gating for all 5 GPIO communities - */ -Method (MPTS, 1, Serialized) -{ - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) -} - -/* - * Method called from _WAK prior to system sleep state wakeup - * Disables dynamic clock gating for all 5 GPIO communities - */ -Method (MWAK, 1, Serialized) -{ - LOCL (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from _SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - LOCL (0) - } -}
-
EricR Lai (Code Review) -
Furquan Shaikh (Code Review)
-
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)