[S] Change in coreboot[master]: soc/intel/meteorlake: Update PMC register definition

[Kapil Porwal (Code Review)]

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70134 )

Change subject: soc/intel/meteorlake: Update PMC register definition
......................................................................

soc/intel/meteorlake: Update PMC register definition

Update GEN_PMCON_B and PMSYNC_TPR_CFG register definition.

BUG=none
TEST=Boot to OS on google/rex.

Signed-off-by: Kapil Porwal 
Change-Id: I9508ecb8fd89fc6519317cf006f177b54d8e6b26
---
M src/soc/intel/meteorlake/include/soc/pmc.h
1 file changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/70134/1

diff --git a/src/soc/intel/meteorlake/include/soc/pmc.h b/src/soc/intel/meteorlake/include/soc/pmc.h
index a56c290..e0a113b 100644
--- a/src/soc/intel/meteorlake/include/soc/pmc.h
+++ b/src/soc/intel/meteorlake/include/soc/pmc.h
@@ -51,6 +51,7 @@
 #define   SLEEP_AFTER_POWER_FAIL	(1 << 0)

#define GEN_PMCON_B			0x1024
+#define   ST_FDIS_LOCK			(1 << 21)
 #define   SLP_STR_POL_LOCK		(1 << 18)
 #define   ACPI_BASE_LOCK		(1 << 17)
 #define   PM_DATA_BAR_DIS		(1 << 16)
@@ -96,7 +97,7 @@
 #define   DSX_EN_LAN_WAKE_PIN		(1 << 0)
 #define DSX_CFG_MASK			(0x1f << 0)

-#define PMSYNC_TPR_CFG			0x18C4
+#define PMSYNC_TPR_CFG			0x18D4
 #define   PCH2CPU_TPR_CFG_LOCK		(1 << 31)
 #define   PCH2CPU_TT_EN			(1 << 26)