Change in coreboot[master]: commonlib: Add new TS for CSE firmware Sync

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59668 )

Change subject: commonlib: Add new TS for CSE firmware Sync
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commonlib: Add new TS for CSE firmware Sync

The patch defines new TS for CSE firmware synchronization.
Also, removes unused TS_FIT_UCODE_LOADED TS.

TEST=Build the code for Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59668
Reviewed-by: Maulik V Vaghela 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/commonlib/include/commonlib/timestamp_serialized.h
1 file changed, 4 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Maulik V Vaghela: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index de3e1bb..3d518b7 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -119,7 +119,8 @@
    TS_ME_ICC_CONFIG_START = 945,
    TS_ME_HOST_BOOT_PREP_DONE = 946,
    TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
-	TS_FIT_UCODE_LOADED = 948,
+	TS_START_CSE_FW_SYNC = 948,
+	TS_END_CSE_FW_SYNC = 949,

/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
    TS_FSP_MEMORY_INIT_START = 950,
@@ -280,7 +281,8 @@
    { TS_ME_ICC_CONFIG_START,	"CSE started to handle ICC configuration"},
    { TS_ME_HOST_BOOT_PREP_DONE,	"CSE sent 'Host BIOS Prep Done' to PMC"},
    { TS_ME_RECEIVED_CRDA_FROM_PMC,	"CSE received 'CPU Reset Done Ack sent' from PMC"},
-	{ TS_FIT_UCODE_LOADED,		"CPU has loaded UCODE/PCODE from FIT"},
+	{ TS_START_CSE_FW_SYNC,		"starting CSE firmware sync"},
+	{ TS_END_CSE_FW_SYNC,		"finished CSE firmware sync"},

/* FSP related timestamps */
    { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },