Hello Nicolas Boichat,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46385
to review the following change.
Change subject: HACK: mt8192: Add SPI support ......................................................................
HACK: mt8192: Add SPI support
Missing pinctrl, so we just hardcode SPI1/SPI5 pins for now.
TODO: There's actually 8 SPI controllers, I think
BUG=none TEST=boot asurada
Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/asurada/bootblock.c 2 files changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46385/1
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 894d566..7c93815 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -39,7 +39,7 @@
config DRIVER_TPM_SPI_BUS hex - default 0x0 + default 0x5
# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. # The number here should be a virtual value as (SPI_BUS_NUMBER + 1). @@ -49,6 +49,6 @@
config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0x2 + default 0x1
endif diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 5dcae8c..3eb05e1 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> +#include <soc/spi.h>
void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + //gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); }
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46385 )
Change subject: HACK: mt8192: Add SPI support ......................................................................
Patch Set 1:
(2 comments)
Hi Yidi, please fix this and correct description, remove the HACK.
https://review.coreboot.org/c/coreboot/+/46385/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46385/1//COMMIT_MSG@6 PS1, Line 6: : HACK: mt8192: Add SPI support : : Missing pinctrl, so we just hardcode SPI1/SPI5 pins for now. : : TODO: There's actually 8 SPI controllers, I think : mb/google/asurada: enable SPI devices
Configure and initialize EC and TPM on Asurada.
https://review.coreboot.org/c/coreboot/+/46385/1/src/mainboard/google/asurad... File src/mainboard/google/asurada/bootblock.c:
https://review.coreboot.org/c/coreboot/+/46385/1/src/mainboard/google/asurad... PS1, Line 10: // please uncomment this - I think we have enough drivers for enabling eint?
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46385 )
Change subject: HACK: mt8192: Add SPI support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46385/1/src/mainboard/google/asurad... File src/mainboard/google/asurada/bootblock.c:
https://review.coreboot.org/c/coreboot/+/46385/1/src/mainboard/google/asurad... PS1, Line 10: //
please uncomment this - I think we have enough drivers for enabling eint?
This line is replaced by gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING);
and GPIO_H1_AP_INT is defined in next patch (mb/google/asurada: Add Chrome OS GPIOs)
I will simply remove this line.
Hello build bot (Jenkins), Nicolas Boichat, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46385
to look at the new patch set (#3).
Change subject: mb/google/asurada: enable SPI devices ......................................................................
mb/google/asurada: enable SPI devices
Configure and initialize EC and TPM on Asurada.
BUG=none TEST=boot asurada
Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/asurada/bootblock.c 2 files changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46385/3
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46385 )
Change subject: mb/google/asurada: enable SPI devices ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46385/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46385/1//COMMIT_MSG@6 PS1, Line 6: : HACK: mt8192: Add SPI support : : Missing pinctrl, so we just hardcode SPI1/SPI5 pins for now. : : TODO: There's actually 8 SPI controllers, I think :
mb/google/asurada: enable SPI devices […]
Ack
https://review.coreboot.org/c/coreboot/+/46385/1/src/mainboard/google/asurad... File src/mainboard/google/asurada/bootblock.c:
https://review.coreboot.org/c/coreboot/+/46385/1/src/mainboard/google/asurad... PS1, Line 10: //
This line is replaced by […]
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46385 )
Change subject: mb/google/asurada: enable SPI devices ......................................................................
Patch Set 3: Code-Review+2
this should be ready for merge, move to base of this chain?
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46385 )
Change subject: mb/google/asurada: enable SPI devices ......................................................................
Patch Set 4: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46385 )
Change subject: mb/google/asurada: enable SPI devices ......................................................................
mb/google/asurada: enable SPI devices
Configure and initialize EC and TPM on Asurada.
BUG=none TEST=boot asurada
Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin yidi.lin@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385 Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/asurada/bootblock.c 2 files changed, 5 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 894d566..7c93815 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -39,7 +39,7 @@
config DRIVER_TPM_SPI_BUS hex - default 0x0 + default 0x5
# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. # The number here should be a virtual value as (SPI_BUS_NUMBER + 1). @@ -49,6 +49,6 @@
config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0x2 + default 0x1
endif diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 5dcae8c..cce1438 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> +#include <soc/spi.h>
void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); }
-
Hung-Te Lin (Code Review) -
Yidi Lin (Code Review)
-
Yu-Ping Wu (Code Review)