Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
soc/intel/fsp_baytrail: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks.
Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/include/reg_script.h M src/lib/reg_script.c D src/soc/intel/fsp_baytrail/Kconfig D src/soc/intel/fsp_baytrail/Makefile.inc D src/soc/intel/fsp_baytrail/acpi.c D src/soc/intel/fsp_baytrail/acpi/device_nvs.asl D src/soc/intel/fsp_baytrail/acpi/globalnvs.asl D src/soc/intel/fsp_baytrail/acpi/gpio.asl D src/soc/intel/fsp_baytrail/acpi/irq_helper.h D src/soc/intel/fsp_baytrail/acpi/irqlinks.asl D src/soc/intel/fsp_baytrail/acpi/irqroute.asl D src/soc/intel/fsp_baytrail/acpi/lpc.asl D src/soc/intel/fsp_baytrail/acpi/lpe.asl D src/soc/intel/fsp_baytrail/acpi/lpss.asl D src/soc/intel/fsp_baytrail/acpi/platform.asl D src/soc/intel/fsp_baytrail/acpi/scc.asl D src/soc/intel/fsp_baytrail/acpi/southcluster.asl D src/soc/intel/fsp_baytrail/acpi/usb.asl D src/soc/intel/fsp_baytrail/acpi/xhci.asl D src/soc/intel/fsp_baytrail/bootblock/bootblock.c D src/soc/intel/fsp_baytrail/chip.c D src/soc/intel/fsp_baytrail/chip.h D src/soc/intel/fsp_baytrail/cpu.c D src/soc/intel/fsp_baytrail/fsp/Kconfig D src/soc/intel/fsp_baytrail/fsp/Makefile.inc D src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c D src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h D src/soc/intel/fsp_baytrail/gfx.c D src/soc/intel/fsp_baytrail/gpio.c D src/soc/intel/fsp_baytrail/i2c.c D src/soc/intel/fsp_baytrail/include/soc/acpi.h D src/soc/intel/fsp_baytrail/include/soc/baytrail.h D src/soc/intel/fsp_baytrail/include/soc/device_nvs.h D src/soc/intel/fsp_baytrail/include/soc/ehci.h D src/soc/intel/fsp_baytrail/include/soc/gfx.h D src/soc/intel/fsp_baytrail/include/soc/gpio.h D src/soc/intel/fsp_baytrail/include/soc/i2c.h D src/soc/intel/fsp_baytrail/include/soc/iomap.h D src/soc/intel/fsp_baytrail/include/soc/iosf.h D src/soc/intel/fsp_baytrail/include/soc/irq.h D src/soc/intel/fsp_baytrail/include/soc/lpc.h D src/soc/intel/fsp_baytrail/include/soc/msr.h D src/soc/intel/fsp_baytrail/include/soc/nvs.h D src/soc/intel/fsp_baytrail/include/soc/pattrs.h D src/soc/intel/fsp_baytrail/include/soc/pci_devs.h D src/soc/intel/fsp_baytrail/include/soc/pcie.h D src/soc/intel/fsp_baytrail/include/soc/pmc.h D src/soc/intel/fsp_baytrail/include/soc/ramstage.h D src/soc/intel/fsp_baytrail/include/soc/romstage.h D src/soc/intel/fsp_baytrail/include/soc/smm.h D src/soc/intel/fsp_baytrail/include/soc/spi.h D src/soc/intel/fsp_baytrail/include/soc/xhci.h D src/soc/intel/fsp_baytrail/iosf.c D src/soc/intel/fsp_baytrail/lpe.c D src/soc/intel/fsp_baytrail/lpss.c D src/soc/intel/fsp_baytrail/memmap.c D src/soc/intel/fsp_baytrail/northcluster.c D src/soc/intel/fsp_baytrail/placeholders.c D src/soc/intel/fsp_baytrail/pmutil.c D src/soc/intel/fsp_baytrail/ramstage.c D src/soc/intel/fsp_baytrail/romstage/Makefile.inc D src/soc/intel/fsp_baytrail/romstage/pmc.c D src/soc/intel/fsp_baytrail/romstage/report_platform.c D src/soc/intel/fsp_baytrail/romstage/romstage.c D src/soc/intel/fsp_baytrail/romstage/uart.c D src/soc/intel/fsp_baytrail/smihandler.c D src/soc/intel/fsp_baytrail/smm.c D src/soc/intel/fsp_baytrail/southcluster.c D src/soc/intel/fsp_baytrail/spi.c D src/soc/intel/fsp_baytrail/tsc_freq.c M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.inc D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf D src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h D src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c D src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c 86 files changed, 3 insertions(+), 14,233 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36982/1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
Patch Set 1: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
Patch Set 1: Code-Review+1
MAINTAINERS:256:F: src/soc/intel/fsp_baytrail/ src/soc/intel/Kconfig:8:source "src/soc/intel/fsp_baytrail/Kconfig"
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
Patch Set 1: Code-Review+1
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
Patch Set 1:
Clean up MAINTAINERS file?
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36982 )
Change subject: soc/intel/fsp_baytrail: Drop support ......................................................................
soc/intel/fsp_baytrail: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks.
Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: David Hendricks david.hendricks@gmail.com --- M src/include/reg_script.h M src/lib/reg_script.c D src/soc/intel/fsp_baytrail/Kconfig D src/soc/intel/fsp_baytrail/Makefile.inc D src/soc/intel/fsp_baytrail/acpi.c D src/soc/intel/fsp_baytrail/acpi/device_nvs.asl D src/soc/intel/fsp_baytrail/acpi/globalnvs.asl D src/soc/intel/fsp_baytrail/acpi/gpio.asl D src/soc/intel/fsp_baytrail/acpi/irq_helper.h D src/soc/intel/fsp_baytrail/acpi/irqlinks.asl D src/soc/intel/fsp_baytrail/acpi/irqroute.asl D src/soc/intel/fsp_baytrail/acpi/lpc.asl D src/soc/intel/fsp_baytrail/acpi/lpe.asl D src/soc/intel/fsp_baytrail/acpi/lpss.asl D src/soc/intel/fsp_baytrail/acpi/platform.asl D src/soc/intel/fsp_baytrail/acpi/scc.asl D src/soc/intel/fsp_baytrail/acpi/southcluster.asl D src/soc/intel/fsp_baytrail/acpi/usb.asl D src/soc/intel/fsp_baytrail/acpi/xhci.asl D src/soc/intel/fsp_baytrail/bootblock/bootblock.c D src/soc/intel/fsp_baytrail/chip.c D src/soc/intel/fsp_baytrail/chip.h D src/soc/intel/fsp_baytrail/cpu.c D src/soc/intel/fsp_baytrail/fsp/Kconfig D src/soc/intel/fsp_baytrail/fsp/Makefile.inc D src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c D src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h D src/soc/intel/fsp_baytrail/gfx.c D src/soc/intel/fsp_baytrail/gpio.c D src/soc/intel/fsp_baytrail/i2c.c D src/soc/intel/fsp_baytrail/include/soc/acpi.h D src/soc/intel/fsp_baytrail/include/soc/baytrail.h D src/soc/intel/fsp_baytrail/include/soc/device_nvs.h D src/soc/intel/fsp_baytrail/include/soc/ehci.h D src/soc/intel/fsp_baytrail/include/soc/gfx.h D src/soc/intel/fsp_baytrail/include/soc/gpio.h D src/soc/intel/fsp_baytrail/include/soc/i2c.h D src/soc/intel/fsp_baytrail/include/soc/iomap.h D src/soc/intel/fsp_baytrail/include/soc/iosf.h D src/soc/intel/fsp_baytrail/include/soc/irq.h D src/soc/intel/fsp_baytrail/include/soc/lpc.h D src/soc/intel/fsp_baytrail/include/soc/msr.h D src/soc/intel/fsp_baytrail/include/soc/nvs.h D src/soc/intel/fsp_baytrail/include/soc/pattrs.h D src/soc/intel/fsp_baytrail/include/soc/pci_devs.h D src/soc/intel/fsp_baytrail/include/soc/pcie.h D src/soc/intel/fsp_baytrail/include/soc/pmc.h D src/soc/intel/fsp_baytrail/include/soc/ramstage.h D src/soc/intel/fsp_baytrail/include/soc/romstage.h D src/soc/intel/fsp_baytrail/include/soc/smm.h D src/soc/intel/fsp_baytrail/include/soc/spi.h D src/soc/intel/fsp_baytrail/include/soc/xhci.h D src/soc/intel/fsp_baytrail/iosf.c D src/soc/intel/fsp_baytrail/lpe.c D src/soc/intel/fsp_baytrail/lpss.c D src/soc/intel/fsp_baytrail/memmap.c D src/soc/intel/fsp_baytrail/northcluster.c D src/soc/intel/fsp_baytrail/placeholders.c D src/soc/intel/fsp_baytrail/pmutil.c D src/soc/intel/fsp_baytrail/ramstage.c D src/soc/intel/fsp_baytrail/romstage/Makefile.inc D src/soc/intel/fsp_baytrail/romstage/pmc.c D src/soc/intel/fsp_baytrail/romstage/report_platform.c D src/soc/intel/fsp_baytrail/romstage/romstage.c D src/soc/intel/fsp_baytrail/romstage/uart.c D src/soc/intel/fsp_baytrail/smihandler.c D src/soc/intel/fsp_baytrail/smm.c D src/soc/intel/fsp_baytrail/southcluster.c D src/soc/intel/fsp_baytrail/spi.c D src/soc/intel/fsp_baytrail/tsc_freq.c M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.inc D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf D src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h D src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c D src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c 86 files changed, 3 insertions(+), 14,233 deletions(-)
Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, but someone else must approve Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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David Hendricks (Code Review)
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HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)
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Werner Zeh (Code Review)