Change in coreboot[master]: soc/intel/alderlake: Implement PMC static function lock

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Subrata Banik, Nick Vaccaro, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63689 )

Change subject: soc/intel/alderlake: Implement PMC static function lock
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Patch Set 2:

(1 comment)

File src/soc/intel/alderlake/lockdown.c:

https://review.coreboot.org/c/coreboot/+/63689/comment/929121e5_446eec02 
PS2, Line 60: 	/* PMSYNC */
            : 	pmc_lock_pmsync();
            : 	/* Lock down ABASE and sleep stretching policy */
            : 	pmc_lock_abase();
            : 
            : 	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
            : 		pmc_lock_smi();
            : 
            : 	if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
            : 		pmc_st_pg_lock();
Noting that this file is basically just setting a few bits in some PMBASE registers, do we need another function to get pmcbase, etc. ? seems like this whole file could be more like 10 lines long?

```
static void pmc_lockdown_cfg(int chipset_lockdown)
{
    setbits32(pmc_mmio_regs() + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
    setbits32(pmc_mmio_regs() + GEN_PMCON_B, SLPSTR_PL_LOCK | ACPI_BASE_LOCK);
    if (chipset_lockdown)
    	setbits8(pmc_mmio_regs() + GEN_PMCON_B, SMI_LOCK);
    if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
    	setbits32(pmc_mmio_regs() + ST_PG_FDIS1, ST_FDIS_LOCK);
}

void soc_lockdown_config(int chipset_lockdown)
{
    pmc_lockdown_cfg(chipset_lockdown);
}
```