Change in coreboot[master]: soc/intel/tgl: Add configurable value for ConfigTdpLevel

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50104 )

Change subject: soc/intel/tgl: Add configurable value for ConfigTdpLevel
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soc/intel/tgl: Add configurable value for ConfigTdpLevel

According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level

Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Nick Vaccaro 
---
M src/soc/intel/tigerlake/chip.h
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
2 files changed, 10 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index d3062cc..edc7160 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -105,6 +105,9 @@
    /* Common struct containing power limits configuration information */
    struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];

+	/* Configuration for boot TDP selection; */
+	uint8_t ConfigTdpLevel;
+
    /* Gpio group routed to each dword of the GPE0 block. Values are
     * of the form PMC_GPP_[A:U] or GPD. */
    uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
index 35cc43b..909ba36 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
@@ -1304,9 +1304,14 @@
 **/
   UINT8                       IsTPMPresence;

-/** Offset 0x0389 - Reserved
+/** Offset 0x0389 - ConfigTdpLevel
+  Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
 **/
-  UINT8                       Reserved17[6];
+  UINT8                       ConfigTdpLevel;
+
+/** Offset 0x038A - Reserved
+**/
+  UINT8                       Reserved17[5];

/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
   Enable PCH PCIe Gen 3 Set CTLE Value.