Hello Karthikeyan Ramasubramanian,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39323
to review the following change.
Change subject: mb/google/dedede: Configure unused GPIOs ......................................................................
mb/google/dedede: Configure unused GPIOs
Configure unused GPIOs as not connected.
BUG=None TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I49886aefc53818a48d0a20210b2739a4fec55e02 --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 37 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39323/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 7b1a9e2..cfa7d54 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -22,11 +22,11 @@ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ /* A7 : SMB_CLK */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), /* A8 : SMB_DATA */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_NC(GPP_A8, NONE), /* A9 : SMB_ALERT_N */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_NC(GPP_A9, NONE), /* A10 : WWAN_EN */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* A11 : TOUCH_RPT_EN */ @@ -46,7 +46,7 @@ /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), /* A19 : PCHHOT_N */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE),
/* B0 : VCCIN_AUX_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -59,25 +59,25 @@ /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_NC(GPP_B5, NONE), /* B6 : PCIE_CLKREQ1_N */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : PCIE_CLKREQ3_N */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_NC(GPP_B10, NONE), /* B11 : PMCALERT_N */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_NC(GPP_B11, NONE), /* B12 : AP_SLP_S0_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR/GSPI0_CS1_N */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_NC(GPP_B14, NONE), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -87,13 +87,13 @@ /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS0_N */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK */ - PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO */ - PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI */ - PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + PAD_NC(GPP_B22, NONE), /* B23 : EC_AP_USB_C1_HDMI_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
@@ -110,9 +110,9 @@ /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* C6 : PMC_SUSWARN_N */ - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + PAD_NC(GPP_C6, NONE), /* C7 : PMC_SUSACK_N */ - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + PAD_NC(GPP_C7, NONE), /* C8 : GPP_C8/UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* C9 : GPP_C9/UART0_TXD */ @@ -202,31 +202,31 @@ /* E2 : CLK_24M_WCAM */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* E3 : GPP_E3/SATA_0_DEVSLP */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + PAD_NC(GPP_E3, NONE), /* E4 : IMGCLKOUT_2 */ - PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), + PAD_NC(GPP_E4, NONE), /* E5 : AP_SUB_IO_2 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* E6 : GPP_E6/IMGCLKOUT_3 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* E7 : GPP_E7/SATA_1_DEVSLP */ - PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), + PAD_NC(GPP_E7, NONE), /* E8 : GPP_E8/SATA_0_GP */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_NC(GPP_E8, NONE), /* E9 : GPP_E9/SML_CLK0/SATA_1_GP */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_NC(GPP_E9, NONE), /* E10 : GPP_E10/SML_DATA0 */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_NC(GPP_E10, NONE), /* E11 : AP_I2C_SUB_INT_ODL */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* E12 : GPP_E12/IMGCLKOUT_4 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : GPP_E13/DDI0_DDC_SCL */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_NC(GPP_E13, NONE), /* E14 : GPP_E14/DDI0_DDC_SDA */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : GPP_E15/DDI1_DDC_SCL */ - PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), /* E16 : GPP_E16/DDI1_DDC_SDA */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), /* E17 : HDMI_DDC_SCL */ @@ -234,7 +234,7 @@ /* E18 : HDMI_DDC_SDA */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_NC(GPP_E19, NONE), /* E20 : CNV_BRI_DT_R */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* E21 : CNV_BRI_RSP */ @@ -287,7 +287,7 @@ /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_SDIO_WP */ - PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + PAD_NC(GPP_G7, NONE),
/* H0 : WWAN_PERST */ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), @@ -296,7 +296,7 @@ /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_NC(GPP_H3, NONE), /* H4 : AP_I2C_TS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : AP_I2C_TS_SCL */ @@ -312,13 +312,13 @@ /* H10 : CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* H11 : GPP_H11/AV_I2S2_SCLK */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), /* H12 : GPP_H12/AVS_I2S2_SFRM/CNF_RF_RESET_N */ - PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), /* H13 : GPP_H13/AVS_I2S2_TXD/MODEM_CLKREQ */ - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_NC(GPP_H13, NONE), /* H14 : GPP_H14/AVS_I2S2_RXD */ - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H14, NONE), /* H15 : I2S_SPK_BCLK */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* H16 : AP_SUB_IO_L */ @@ -339,9 +339,9 @@ /* R3 : I2S_HP_MIC */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), /* R4 : GPP_R04/HDA_RST_N */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R4, NONE), /* R5 : GPP_R05/HDA_SDI1/AVS_I2S1_RXD */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), /* R6 : I2S_SPK_LRCK */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), /* R7 : I2S_SPK_AUDIO */ @@ -356,9 +356,9 @@ /* S3 : DMIC1_DATA */ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* S4 : GPP_S04/SNDW1_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + PAD_NC(GPP_S4, NONE), /* S5 : GPP_S05/SNDW1_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + PAD_NC(GPP_S5, NONE), /* S6 : DMIC0_CLK */ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), /* S7 : DMIC0_DATA */ @@ -383,9 +383,9 @@ /* GPD8 : WLAN_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 : AP_SLP_WLAN_L */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + PAD_NC(GPD9, NONE), /* GPD10 : AP_SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + PAD_NC(GPD10, NONE), };
/* Early pad configuration in bootblock */
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39323 )
Change subject: mb/google/dedede: Configure unused GPIOs ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39323/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39323/1//COMMIT_MSG@9 PS1, Line 9: Configure unused GPIOs as not connected. Fits in the commit message summary.
https://review.coreboot.org/c/coreboot/+/39323/1//COMMIT_MSG@10 PS1, Line 10: According to schematics?
Karthik Ramasubramanian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39323 )
Change subject: mb/google/dedede: Configure unused GPIOs ......................................................................
Abandoned
The changes here are squashed into https://review.coreboot.org/c/coreboot/+/39114. So abandoning this change. Sorry Paul Menzel that I did not abandon it earlier and made you review this redundant CL.
-
Karthik Ramasubramanian (Code Review) -
Paul Menzel (Code Review)