Change in coreboot[master]: soc/intel/alderlake: Implement PCH lock down configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63692 )

Change subject: soc/intel/alderlake: Implement PCH lock down configuration
......................................................................

soc/intel/alderlake: Implement PCH lock down configuration

This patch implements a function to enable IOSF Primary Trunk Clock
Gating.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik 
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
---
M src/soc/intel/alderlake/lockdown.c
1 file changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63692/1

diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c
index 4ee223e..bca48b0 100644
--- a/src/soc/intel/alderlake/lockdown.c
+++ b/src/soc/intel/alderlake/lockdown.c
@@ -8,14 +8,20 @@

#include <device/mmio.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
 #include <intelblocks/pmc_ipc.h>
 #include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <stdint.h>

#define PMC_IPC_CPU_STRAP		0xB1
 #define  PMC_IPC_CPU_STRAP_LOCK	0

+/* Trap status Register */
+#define PCR_PSTH_CTRLREG		0x1d00
+#define   PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
+
 static void pmc_lock_pmsync(void)
 {
    uint8_t *pmcbase;
@@ -102,8 +108,19 @@
    }
 }

+static void pch_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
 void soc_lockdown_config(int chipset_lockdown)
 {
    /* PMC lock down configuration */
    pmc_lockdown_cfg(chipset_lockdown);
+	/* PCH lock down configuration */
+	pch_lockdown_cfg();
 }