Change in coreboot[master]: mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware

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Paul Menzel (Code Review)

7 Mar 2020 7 Mar '20

11:16 a.m.

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware ......................................................................

mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware

Here is the relevant output of `superiotool` for the global control registers:

Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM

The serial console still does not work.

Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/asus/f2a85-m/bootblock.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39371/1

diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index 3d980a6..cbd6e3a 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -15,6 +15,7 @@ */

#include <bootblock_common.h> +#include <device/pnp_ops.h> #include <device/pnp_type.h> #include <amdblocks/acpimmio.h> #include <stdint.h> @@ -47,8 +48,21 @@

static void superio_init_m_pro(void) { + pnp_devfn_t global_dev = PNP_DEV(0x2e, 0); pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);

+ pnp_write_config(global_dev, 0x13, 0xff); + pnp_write_config(global_dev, 0x14, 0xff); + pnp_write_config(global_dev, 0x1a, 0x0a); + pnp_write_config(global_dev, 0x1b, 0x28); + pnp_write_config(global_dev, 0x1c, 0x00); + pnp_write_config(global_dev, 0x1d, 0x10); + pnp_write_config(global_dev, 0x22, 0xdf); + pnp_write_config(global_dev, 0x2a, 0x48); + pnp_write_config(global_dev, 0x2b, 0x20); + pnp_write_config(global_dev, 0x2c, 0x00); + pnp_write_config(global_dev, 0x2f, 0x01); + nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); }

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Paul Menzel (Code Review)

13 Oct 13 Oct

5:43 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

Patch Set 13:

This change is ready for review.

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 13 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-Comment-Date: Tue, 13 Oct 2020 15:43:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Angel Pons (Code Review)

17 Oct 17 Oct

2:53 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

Patch Set 14: Code-Review+1

(3 comments)

https://review.coreboot.org/c/coreboot/+/39371/3//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/39371/3//COMMIT_MSG@11 PS3, Line 11: Here is the relevant output of `superiotool` for the global control : registers running the vendor firmware: : : Found Nuvoton NCT6779D (id=0xc562) at 0x2e : Register dump: : idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f : val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 : def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM

...

I don't think this is really needed

Not a big deal

https://review.coreboot.org/c/coreboot/+/39371/5/src/mainboard/asus/f2a85-m/... File src/mainboard/asus/f2a85-m/bootblock.c:

https://review.coreboot.org/c/coreboot/+/39371/5/src/mainboard/asus/f2a85-m/... PS5, Line 47: pnp_write_config

...

You may want to use the functions from CB:42134

Ack

https://review.coreboot.org/c/coreboot/+/39371/5/src/mainboard/asus/f2a85-m/... PS5, Line 51: printk(BIOS_DEBUG, "old reg: 0x%x", reg);

...

This is futile as the console is only initialized after bootblock_mainboard_early_init().

Ack

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 14 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-Comment-Date: Sat, 17 Oct 2020 12:53:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber nico.h@gmx.de Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Patrick Georgi (Code Review)

20 Oct 20 Oct

1:54 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39371/14/src/mainboard/asus/f2a85-m... File src/mainboard/asus/f2a85-m/Kconfig:

https://review.coreboot.org/c/coreboot/+/39371/14/src/mainboard/asus/f2a85-m... PS14, Line 17: SUPERIO_NUVOTON_NCT6779D_COM_A has been renamed to SUPERIO_NUVOTON_COMMON_COM_A in commit 00e58c35c62dbd6c2b20980d594b2b9d1153aa45

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 14 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-CC: Patrick Georgi pgeorgi@google.com Gerrit-Comment-Date: Tue, 20 Oct 2020 11:54:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Paul Menzel (Code Review)

4:57 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Hello build bot (Jenkins), Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39371

to look at the new patch set (#15).

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Currently, the serial console does not work.

With the serial port enabled in the vendor firmware, `superiotool` outputs the global control register values below.

UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`. This changes the default value 0xc0 to 0x40.

Note, due configuring the system as legacy free with `HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in `FchInitResetLpcProgram()`.

coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31

APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET

`AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only when coreboot enables the LPC controller again in ramstage, serial output continues.

PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 […] done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms Initializing devices... CPU_CLUSTER: 0 init […]

Note, due to incorrect Super I/O configuration in the devicetree, the boot hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This will be fixed in follow-up commits.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39371/15

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 15 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-CC: Patrick Georgi pgeorgi@google.com Gerrit-MessageType: newpatchset

Angel Pons (Code Review)

7:08 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

Patch Set 15: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/39371/14/src/mainboard/asus/f2a85-m... File src/mainboard/asus/f2a85-m/Kconfig:

https://review.coreboot.org/c/coreboot/+/39371/14/src/mainboard/asus/f2a85-m... PS14, Line 17: SUPERIO_NUVOTON_NCT6779D_COM_A

...

has been renamed to SUPERIO_NUVOTON_COMMON_COM_A in commit 00e58c35c62dbd6c2b20980d594b2b9d1153aa45

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 15 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-CC: Patrick Georgi pgeorgi@google.com Gerrit-Comment-Date: Tue, 20 Oct 2020 17:08:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi pgeorgi@google.com Gerrit-MessageType: comment

Angel Pons (Code Review)

21 Oct 21 Oct

2:29 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Currently, the serial console does not work.

With the serial port enabled in the vendor firmware, `superiotool` outputs the global control register values below.

UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`. This changes the default value 0xc0 to 0x40.

Note, due configuring the system as legacy free with `HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in `FchInitResetLpcProgram()`.

coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31

APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET

`AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only when coreboot enables the LPC controller again in ramstage, serial output continues.

Note, due to incorrect Super I/O configuration in the devicetree, the boot hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This will be fixed in follow-up commits.

TEST=Receive (some) coreboot log messages over the serial console. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/f2a85-m/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)

Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 8413cd3..27d5517 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -14,6 +14,7 @@ select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO + select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO select BOARD_ROMSIZE_KB_8192 select GFXUMA

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 16 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-CC: Patrick Georgi pgeorgi@google.com Gerrit-MessageType: merged

9elements QA (Code Review)

3:55 p.m.

New subject: Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable UART A in Super I/O

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39371 )

Change subject: mb/asus/f2a85-m_pro: Enable UART A in Super I/O ......................................................................

Patch Set 16:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/2/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : FAIL : https://lava.9esec.io/r/23994 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/23993 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/23992 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/23991 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/23989 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/23988

Please note: This test is under development and might not be accurate at all!

-- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 16 Gerrit-Owner: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Nico Huber nico.h@gmx.de Gerrit-CC: Patrick Georgi pgeorgi@google.com Gerrit-Comment-Date: Wed, 21 Oct 2020 13:55:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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9elements QA (Code Review)
Angel Pons (Code Review)
Patrick Georgi (Code Review)
Paul Menzel (Code Review)